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FS401, FS403 PC to TV Video Scan Converters
Features
Note: Covered under US Patent # 5,862,268, # 5,905,536, # 5,966,184 and/or patents pending.
* * * * * *
Frame rate Conversion Programmable 2D scaling Pan and Zoom Advanced 2-D flicker filter Frame-store memory controller Supports Multiple Progressive Input Resolutions -Minimum 640x 400 -Maximum 2048 x 1536 * Supports Interlaced Input -XGA and above * Input refresh rates up to 150Hz * Multiple Output Standards -NTSC, NTSC-EIAJ, PAL-B/G/H/I -Composite, S-Video, SCART -RGB, YUV Standard NTSC and PAL Super NTSC & PAL VGA Progressive SVGA Progressive NTSC Progressive PAL 100Hz Interlaced * Automatically detects input active video area * Automatically selects the best output and scaling for any input resolution * Programmable sharpness, brightness, contrast and color saturation * Customizable On Screen Display via glueless integration with Zilog and Philips OSD Microprocessors (FS403) * C, H, and V Sync tri-state outputs * H and V Sync monitoring for DPMS Support * Exceeds all PC97 and PC98 requirements * General Purpose Output Pins (2 on FS401, 7 on FS403) * Genlock (FS403) * 8-bit A/D converters with frequency adaptive input filtering support * 10-bit output D/A converters * Digital RGB Inputs (FS403) * I2C compatible port controls (SIO) * 100 pin PQFP (FS401) * 128 pin PQFP (FS403) * 3.3V operation * RoHS Compliant 1
JANUARY 24, 2007
Description
The FS400 family is a fourth generation video scan converter. It accepts many input resolutions and rates and converts them to NTSC or PAL standards compliant with SMPTE-170M and CCIR-656 standards. Also available as output options are VGA 640 x 480 at 60Hz progressive, SVGA 800 x 600 at 60Hz progressive, and 100 Hz interlaced. The chip has a programmable down scaler to fit the incoming resolution to the output display format. Within the FS400 are capture and encoder engines separated by the frame buffer memory controller. Required external components are minimal: a single 16M SDRAM memory, clocks and passive parts. Analog progressive RGB inputs are digitized and converted to the YUV 4:2:2 format. Vertical scaling and flicker filtering are implemented at the computer frame rate ahead of the frame store interface. Interlaced input is supported for XGA resolution and above. In this mode, only the first field is processed. The Flicker Filter is an advanced 2 dimensional filter that enhances text quality. Flicker Filter parameters are programmable to allow user tradeoffs between flicker and sharpness. The FS400 family contains controls for programmable sharpness, brightness, contrast, and color saturation. These controls allow output to be tuned to match user desires and tastes. Frame rate conversion is implemented by a Frame Store Controller that interfaces with an external SDRAM frame store memory. YUV 4:2:2 data is recovered from the memory at the outgoing frame rate. Data is scaled prior to the
COPYRIGHT (c)1999, 2000, 2003 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
digital video encoder that generates Y/C and Composite Video outputs. For RGB and YUV outputs, the encoder may be bypassed via a YUV to RGB transcoder for SCART compatible video, and for output to VGA or SVGA displays. The FS400 has built in capability to automatically detect the incoming video mode and automatically select optimal sampling and scaling parameters. The chip can detect the location of the active video in the input, and can automatically center the input on the TV screen. All parameters can be read and written via the SIO serial port. The FS403 has support for glueless integration with Zilog and Philips On Screen Display (OSD) microcontrollers. The OSD interface allows a customized on
screen user interface that can contain opaque or halftone video backgrounds. The FS403 has direct digital inputs, bypassing the built-in ADCs. Power is derived from +3.3V digital and analog supplies. Packages are 100-lead (FS401) or 128-lead (FS403) Plastic Quad Flat Pack (PQFP).
Applications
* * * * * *
PC video out PC ready TV's Video Text Displays Web Appliances PC-to-TV Scan Converter Peripherals Video Kiosks
Architectural Block Diagram
ADC_SEL R_DIG G_DIG B_DIG Built In Pattern Multiplexer VSYNC HSYNC CSYNC FLP_RST Video Encoder YUV/RGB Matrix 10 Bit DAC 10 Bit DAC 10 Bit DAC LUMA_R_V CVBS_G_Y CHROMA_B_U
Gain
RED GRN BLU
8 Bit ADC 8 Bit ADC 8 Bit ADC Vertical Scaler VGA PLL Horizontal Scaler /3 Flicker Filter VGA Cache TV Cache RGB/YUV Matrix OSD Overlay
Clamp
RGB_OSD
HALFTONE
VGA_HSYNC VGA_VSYNC Clock Generator
DRAM PLL
Xtal_N Xtal_P
Serial Bus Interface
Embedded Processor
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JANUARY 24, 2007 COPYRIGHT (c) 1999, 2000, 2003 FOCUS ENHANCEMENTS, INC.
NTSC_PAL
SIO_DATA
4 BUTTON
SIO_CLK
EXT_CPU
SIO_10/7
SIO_A0
OSD_EN
External Sync DRAM Memory
Multiplexer
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
Contents
1. Architectural Overview .................................... 5 1.1 Video Capture Engine............................. 5 1.2 Frame Store Memory Controller ............. 6 1.3 Video Encoder Engine ............................ 6 1.4 Serial Control Port .................................. 6 1.5 Typical System Configurations ............... 7 1.5.1 External Scan Converter .................... 7 1.5.2 Embedded Television Interface.......... 8 1.5.3 Deleted ............................................... 8 1.5.4 Professional and Pro-Consumer Video Designs ................................................. 9 2. Pin Assignments............................................ 10 2.1 100-Lead PQFP Package (FS401)....... 10 2.2 128-Lead PQFP Package (FS403)....... 11 3. Pin Descriptions ............................................ 12 4. Control Register Definitions........................... 17 4.1 Control Register Functions ................... 17 4.2 Internal Micro-Controller Programming ..................................................... 18 4.2.1 Input Calibration ............................... 18 4.2.1.1 Auto Input Calibration .............. 18 4.2.1.2 Manual Input Calibration.......... 19 4.2.1.3 Input Calibration Tables........... 20 4.2.2 Output Calibration ............................ 20 4.2.3 Zoom ................................................ 20 4.2.4 Panning ............................................ 21 4.2.5 Picture Control.................................. 21 4.2.6 Video Mode Changes....................... 22 4.2.7 By-passing the Internal MicroController ....................................................... 22 4.2.8 Special Internal Micro-Controller SIO Requirements......................................... 24 4.3 Disabling the Internal MicroController ........................................................... 24 4.4 Control Register Definitions.................. 25 4.5 Control Registers Definitions ................ 28 4.5.1 IHO - Input Horizontal Offset ............ 28 4.5.2 IVO - Input Vertical Offset ................ 29 4.5.3 IHAW - Horizontal Active Width ....... 30 4.5.4 ILS - Input Lines Stored.................... 31 4.5.5 IHS - Input Horizontal Samples........ 32 4.5.6 IHC - Input Horizontal Count ............ 33 4.5.7 IVC - Input Vertical Count................. 34 4.5.8 VSC - Vertical Scaling Coefficient ... 35 4.5.9 CR - Command Register .................. 36 4.5.10 SR - Status Register ................... 37 4.5.11 CRE - Command Register Extended 38 4.5.12 Start Horizontal Active VGA......... 39 4.5.13 End Horizontal Active VGA .......... 40 4.5.14 Start Vertical Active VGA ............. 41 4.5.15 End Vertical Active VGA .............. 42 4.5.16 Active Video Threshold ................ 43 4.5.17 OHO - Output Horizontal Offset ... 44 4.5.18 OVO - Output Vertical Offset....... 45 4.5.19 HSC - Horizontal Scaling Coefficient 46 3
JANUARY 24, 2007 COPYRIGHT (c) 1999, 2000, 2003 FOCUS ENHANCEMENTS, INC.
4.5.20 Contrast Coefficient ......................47 4.5.21 Brightness Coefficient...................48 4.5.22 Sharpness Coefficient ..................49 4.5.23 Flicker Filter Coefficient ................50 4.5.24 Color Saturation Coefficient..........51 4.5.25 General Purpose Outputs.............52 4.5.26 SCR - Software Control Register 53 4.5.27 SSR - Software Status Register ..55 4.5.28 HCRS - Hardware Control Register Shadow............................................56 4.5.29 HCRES - Hardware Control Register Extended Shadow ...........................57 4.5.30 HPO - Horizontal Position Offset 58 4.5.31 VPO - Vertical Position Offset......59 4.5.32 HSS - Horizontal Scale Step........60 4.5.33 VSS - Vertical Scale Step ............61 4.5.34 HPP - Horizontal Pan Position.....62 4.5.35 VPP - Vertical Pan Position .........63 4.5.36 TVP - TV Pixels............................64 4.5.37 TVL - TV Lines .............................65 4.5.38 CCR - Configuration Command Register 66 4.5.39 CDR - Configuration Data Register 67 4.5.40 HOHOS - Hardware Output Horizontal Offset Shadow ..............................68 4.5.41 HOVOS - Hardware Output Vertical Offset Shadow...................................69 4.6 Configuration Values .............................70 Addr ....................................................................70 5. Functional Description ...................................75 5.1 Capture Engine .....................................75 5.1.1 Timing and Control............................75 5.1.2 Clamps ..............................................76 5.1.3 Analog-to-Digital Converters.............76 5.1.4 24-bit Digital RGB Port (FS403 only) 77 5.1.5 Built In Pattern Generator .................77 5.1.6 Digital RGB Multiplexer .....................78 5.1.7 RGB Gain..........................................78 5.1.8 RGB/YUV Matrix ...............................78 5.1.9 Vertical Scaler ...................................78 5.1.10 Flicker Filter ..................................78 5.2 Frame Store Controller..........................80 5.2.1 SDRAM Interface ..............................81 5.2.2 Phase Locked Loop ..........................81 5.2.3 Input Offset and Size Control............81 5.2.4 Output Offset and Size Control .........82 5.2.5 Freeze Frame....................................82 5.2.6 Zoom .................................................83 5.3 Encoder Engine .....................................83 5.3.1 Timing and Control............................83 5.3.2 Horizontal Scaler...............................84 5.3.3 Digital Video Encoder .......................84 5.3.4 YUV/RGB Matrix ...............................84
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
5.3.5 Digital-to-Analog Converters ............ 85 5.3.6 On-Screen Display (FS403 only) ..... 85 5.4 Serial Control Port (R-Bus)................... 85 5.4.1 Data Transfer via Serial Interface .... 88 5.4.2 Serial Interface Read/Write Examples....................................................... 88 5.4.2.1 Write to one control register .... 88 5.4.2.2 Write to two consecutive control registers......................................... 89 5.4.2.3 Read from one control register 89 5.4.2.4 Read from two consecutive data registers ............................................ 89 5.5 Embedded Microprocessor................... 89 6. Specifications ................................................ 90 6.1 Absolute Maximum Ratings.................. 90 6.2 Operating Conditions ............................ 91 6.3 Electrical Characteristics ...................... 92 6.4 Switching Characteristics ..................... 93 6.5 System Performance Characteristics ... 94 7. Application Notes .......................................... 95 7.1 Circuit Example - PC ............................ 95 7.2 FS400 Design and Layout Considerations................................................... 96 7.2.1 Video Input to A-D Converters ......... 96 7.2.2 Input ADC Phase Lock Loop............ 96 7.2.3 Memory Clock Phase Lock Loop ..... 96 7.2.4 External SDRAM Interface ............... 96 7.2.5 HSYNC and VSYNC ........................ 96 7.2.6 Video Output Filters.......................... 97 7.2.7 Analog Power Supply Bypassing, Filtering, and Isolation ................................... 97 7.2.8 Power and Ground ........................... 97 7.3 Interfacing to the FS400 in a Mixed Voltage Environment ......................................... 98 7.3.1 5 to 3.3 Volt Translation ................... 98 7.3.2 SIO Bus Interfacing .......................... 98 8. Mechanical Dimensions .............................. 101 8.1 100-Lead PQFP (KH) Package FS401LF .......................................................... 101 8.2 128-Lead PQFP Package, FS403 LF. 102 9. Revision History .......................................... 103 10. Ordering Information ............................... 104 10.1 Package Markings: ............................. 104
Figures
Figure 1: External Scan Converter Block Diagram............................................................7 Figure 2: Embedded Television Design Block Diagram............................................................8 Figure 3: Deleted .....................................................8 Figure 4: Professional & Pro-Consumer Video Design Block Diagram .....................................9 Figure 5. Functional Block Diagram ......................75 Figure 6. FAZE Sets ADCK Sampling Edge on Incoming Pixels ..............................................77 Figure 7: BiPGEN Image .......................................77 Figure 8: Two Dimensional Flicker Filter Response (FLK=0,4,8,12,16,20; SHP=0) ......79 Figure 9: FLK = 16, SHP = 8; Response at Horizontal, 14, 27, 45 Degrees ......................79 Figure 10: FLK = 16, SHP = 16; Response at Horizontal, 14, 27, 45 Degrees ......................80 Figure 11. Timing Parameter Definition, SDRAM Interface .........................................................81 Figure 12. Input Offset and Size Definitions ..........82 Figure 13. Output Horizontal and Vertical Offset Definitions ......................................................82 Figure 14. Zoomed image showing offsets............83 Figure 15. RREF and VTIN Setup..............................85 Figure 16. Serial Port Read/Write Timing..............86 Figure 17. Serial Interface - Typical Byte Transfer ..........................................................86 Figure 18. 7-bit Slave Address with Read/Write\ Bit ...................................................................87 Figure 19. 10-bit address transfer, upper two bits..................................................................87 Figure 20. 10-bit address transfer, lower eight bits..................................................................87 Figure 21. Video Filter Response ..........................95 Figure 22. Video Filter Delay .................................95 Figure 23. 5 to 3.3 Volt Translation using a Resistor ..........................................................98 Figure 24. 5 to 3.3 Volt Translation using a MOSFET Q1 = BSS138, D1 = 1N4148..........98 Figure 25. SIO Translation Using Long-tail Resistors D1 = 1N4148..................................99 Figure 26. SIO Translation Using Current Mirrors D1 = 1N4148, Q1 = 2N3906, Q2 = 2N3904...........................................................99 Figure 27. SIO (Open Collector) Translation using a MOSFET Q1 = BSS138 ..................100
Tables
Table 1. Pin Designations (FS401, 100-pin package)........................................................ 10 Table 2. Pin Designations (FS403, 128-pin package)........................................................ 11 Table 3. Control Register Map .............................. 25 Table 4. Clock Connections ................................... 83 Table 5. Serial Port Addresses .............................. 88
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JANUARY 24, 2007 COPYRIGHT (c) 1999, 2000, 2003 FOCUS ENHANCEMENTS, INC.
1. Architectural Overview
Overall design principles are included in this section. Details of how to use and setup the FS400 are included in the Functional Description section, starting on page 75. RGB video inputs are asynchronously converted to either NTSC/PAL, YUV or RGB video formats. Architecturally, the FS400 is divided into five major sections: 1. 2. 3. 4. 5. Video Capture Engine Clock Processor Frame Store Controller Video Encoder Engine Serial Bus Interface
Besides power and a few external passive components, the FS400 requires only a single 16M external SDRAM and external clocks to implement a high quality video scan converter. Either analog or digital inputs (FS403 only) with separate horizontal and vertical sync signals are accepted. Analog VGA video must be RGB. Digital video (FS403 only) must be 24-bit RGB clocked by external clock, VGACK_IN. A wide range of resolution formats can be accepted, including common standards such as 320x240, 640x400, 720x400, 640x480, 800x600, 832x624, 1024x768, 1152x864, 1280x1024, and 1600x1200. Incoming RGB signals are converted to either the NTSC or PAL TV Standards, 100Hz PAL, or progressive scan VGA, SVGA, or NTSC. Output video format can be selected to be either composite and Y/C (NTSC and PAL only), or RGB or YUV (all standards). Incoming frame rate may range to over 150 Hz according to the table below. The Video Capture engine runs asynchronously relative to the Video Encoder Engine. An external frame store memory separates the two engines with write and read access controlled by the FS400. Transformation operations include overscan, underscan, pan and zoom. Scaling operations are separated by the frame store with vertical down-sampling incorporated into the Capture Engine and horizontal up-sampling incorporated into the Encoder Engine.
1.1 Video Capture Engine
Triple 8-bit A/D converters digitize the analog RGB inputs at rates of up to 50 MHz. Internal A/D sample clock, ADCK is derived from a phase locked loop referenced to the leading edge of horizontal sync. Either positive or negative sync polarity is accepted. The selected input (A/D converter outputs or digital RGB) is transcoded by the color matrix into a 16-bit YCRCB 4:2:2 format. A vertical scaler filters the number of incoming video lines by the selected scaling factor. A flicker filter averages lines to eliminate flicker between lines or boundaries. The Video Capture Engine is programmable as to the number of horizontal samples it takes. The limiting factor in the sample rate is the A/D Converters. By programming fewer samples per line, higher incoming data rates can be accommodated. The following table illustrates the capability: Active Samples Maximum Line Frequency 640 x 480 800 x 600 1024 x 768 1152 x 864 1280 x 1024 1600 x 1200 720 CCIR 601 56kHz 106Hz 89Hz 70Hz 59Hz 53Hz 44Hz 640 63kHz 119Hz 100Hz 78Hz 66Hz 59Hz 50Hz 500 80kHz 152Hz 128Hz 100Hz 85Hz 76Hz 64Hz
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JANUARY 24, 2007 COPYRIGHT (c)1999, 2000, 2003 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
1.2 Frame Store Memory Controller
Inserted between the capture and the encoder engines the frame store has two functions: 1) to act as a reservoir of pixels to match the incoming frame rate to the outgoing field or frame rate; 2) to support vertical scaling by allowing lines to be written into the frame store intermittently, but read out at a constant rate. Frame store clock, FS_CK is derived from the OSC1 clock by a second phase locked loop.
1.3 Video Encoder Engine
Pixels are retrieved from the external frame store memory asynchronously relative to the incoming frames. Outgoing video timing is set to the selected TV (NTSC or PAL) or progressive scan standard. Incoming data sampling is normally set to fill complete lines in the Frame Store Memory. Horizontal scaling is applied to pixels exiting the Frame Store. Pixels may be routed through either a digital video encoder or a YCRCBto-RGB transformation matrix. Either output is connected to a triple 10-bit D/A converter to generate the video output that may be Composite Video and Y/C, RGB or YUV. Encoder Engine timing is derived from many clock sources. These standards are shown below. Encoder Standard NTSC PAL RGB NTSC RGB PAL Super RGB NTSC Super RGB PAL VGA SVGA Progressive NTSC 100Hz PAL Total Pixels 910 1135.0064 910 1135 1280 1280 800 1024 910 1135 Total Lines 525 625 525 625 525 625 525 625 525 625 Vertical Mode 60I 50I 60I 50I 60I 50I 60P 60P 60P 100I Clock Rate 14.318 MHz 17.734 MHz 14.318 MHz 17.734 MHz 20.140 MHz 20.000 MHz 25.175 MHz 38.400 MHz 28.636 MHz 35.468 MHz Line Freq. 15.73 KHz 15.62 KHz 15.73 KHz 15.62 KHz 15.73 KHz 15.62 KHz 31.5 KHz 37.5 KHz 31.5 KHz 31.25 KHz
1.4 Serial Control Port
FS400 setup is programmed by 39 16-bit registers that are accessible via the I2C compatible serial port (SIO). Status and Revision ID can also be read from the registers. Note: I2C is a registered trademark of Philips Corporation. The FS400 SIO bus is similar but not identical to Philips I2C bus.
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JANUARY 24, 2007 COPYRIGHT (c) 1999, 2000, 2003 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
1.5 Typical System Configurations
1.5.1 External Scan Converter
The FS403 has been optimized for scan converter designs. It provides a maximum amount of flexibility while minimizing system cost. When combined with a Zilog Z902xx Family or Philips P8xC055/145/845 Families, the FS403 provides overlaid On-Screen Display pixels specified by the programmer without any additional external components thus minimizing expense, complexity, and size while maximizing flexibility and features.
SDRAM
VGA Red VGA Blue VGA Green VGA HS VGA VS
OSD Clk Crystal
Composite
FS403
S Video SCART
VSync RGB SIO HSync Blank
Microcontroller with OSD
Figure 1: External Scan Converter Block Diagram
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JANUARY 24, 2007 COPYRIGHT (c) 1999, 2000, 2003 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
1.5.2 Embedded Television Interface
The FS401 has been optimized for television designs. With its built in microprocessor, the FS401 can run freely with minimal control from the television processor while providing complete plug-n-play capability. Simple commands can be sent to the FS401 via the SIO bus to implement remote control functions such as zoom, pan, sizing, positioning, and video quality control (such as brightness, contrast, saturation, flicker, and sharpness). The only components required are the FS401 and a single SDRAM for a truly minimal incremental system cost.
SDRAM
VGA Red VGA Blue VGA Green VGA HS VGA VS
Crystal
Figure 2: Embedded Television Design Block Diagram
TV Red
FS401
TV Blue TV Green CSync
1.5.3 Deleted
Figure intentionally left blank.
Figure 3: Deleted
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JANUARY 24, 2007 COPYRIGHT (c) 1999, 2000, 2003 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
1.5.4 Professional and Pro-Consumer Video Designs
In the Professional and Pro-Consumer Video Market, Video quality, video timing accuracy, and Genlock are very important features. Also the system will use external ADCs and PLLs of the highest quality. Genlock to an external studio Black Burst (black screen TV picture) will be used to synchronize the scan converter to the rest of the video studio.
SDRAM
PLL
R G B VGA HS VGA VS Black Burst
8 Bit ADC 8 Bit ADC 8 Bit ADC
Composite
FS403
S Video Component
Genlock
4fsc FLP_Rst
Figure 4: Professional & Pro-Consumer Video Design Block Diagram
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JANUARY 24, 2007 COPYRIGHT (c) 1999, 2000, 2003 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
80
51
81
50
100
31
1
30
2. Pin Assignments
2.1 100-Lead PQFP Package (FS401)
Table 1. Pin Designations (FS401, 100-pin package)
Pin 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. Name VDDPF OSC1 OSC1BUF OSC2 OSC2BUF VSS VSSDA CCOMP IREF VDDDA CBYPASS Y/R/V VDDDA VSSDA CVBS/G/Y VDDDA C/B/U VDDDA VDD CSYNC VSS VSS SIOCLK SIODATA SIOA10/7 SIOA0 VDD Reserved (VSS) Reserved (VSS) RESET Pin 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. Name TV_VSYNC TV_HSYNC VDDAD VSSAD VSSAD R_IN VDDAD VDDAD G_IN VSSAD VTOUT VADCREF VSSAD B_IN VDDAD CLAMP_REF VDDPA VSSPA VS_IN HS_IN Pin 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80. Name VSS EXTVGASEL\ VGACLKIN VDD VSS VSS DQM WE\ INTCPUEN RAS\ CAS\ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 VDD VSS D12 D13 D14 D15 VSS Pin 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96. 97. 98. 99. 100. Name GPO6 VDD A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 VDD GPO0 VSSPF RAMCK_SEL\ RAMCK_OUT RAMCK_IN
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JANUARY 24, 2007 COPYRIGHT (c) 1999, 2000, 2003 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
2.2 128-Lead PQFP Package (FS403)
Table 2. Pin Designations (FS403, 128-pin package)
Pin 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. Name OSC1 OSC1BUF OSC2 OSC2BUF VSS VSSDA CCOMP IREF VDDDA CBYPASS Y/R/V VDDDA VSSDA CVBS/G/Y VDDDA C/B/U VDDDA VDD OSDCLK CSYNC VSS VSS EXADSEL G6/OSDB G5/OSDG G4/OSDR G7/OSDHT VSS SIOCLK SIODATA SIOA10/7 SIOA0 Pin 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. 64. Name VDD Reserved (VSS) FLP_RST Reserved (VSS) RESET R0/TV_VSYNC R1/TV_HSYNC R2/OSDEN R3 VDDAD VSSAD VSSAD R_IN VDDAD VDDAD G_IN VSSAD VTOUT VADCREF VSSAD B_IN VDDAD CLAMP_REF R4 R5 R6 R7 VDDPA VSSPA VS_IN HS_IN VSS Pin 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96. Name VGACLKDIV EXTVGASEL\ VGACLKIN VDD VSS G3 G2 G1 G0 VSS DQM WE\ INTCPUEN RAS\ CAS\ VDD D0 D1 D2 D3 D4 D5 D6 D7 VSS VDD D8 D9 D10 D11 VDD VSS Pin 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. 112. 113. 114. 115. 116. 117. 118. 119. 120. 121. 122. 123. 124. 125. 126. 127. 128. Name D12 D13 D14 D15 VSS B7/GPO7 B6/GPO6 B5/GPO5 B4/GPO4 VDD A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 VDD B3/GPO3 B2/GPO2 B1/GPO1 B0/GPO0 VSSPF RAMCK_SEL\ RAMCK_OUT RAMCK_IN VDDPF
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JANUARY 24, 2007 COPYRIGHT (c) 1999, 2000, 2003 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
3. Pin Descriptions
Pin Name Clocks OSC1 Pin Number
FS401/FS403
Type/Value
Pin Function Description
2/1
TTL input
OSC1BUF
3/2
LVTTL output TTL input
OSC2
4/3
OSC2BUF
5/4
LVTTL output TTL input TTL input
HS_IN VS_IN
50/63 49/62
Oscillator Number 1. Default clock input to the encoder. Input from an external oscillator; or one pin of a crystal connected between OSC1 and OSC1BUF. NTSC subcarrier frequency can be derived from this 4fSC clock. OSC1 must be connected (see Table 4. Clock Connections). Oscillator 1 Buffer. If a crystal is used, one pin is connected to OSC1, the other to OSC1BUF. Float this pin if OSC1 is connected to an oscillator. Oscillator Number 2. Input from an external oscillator; or one pin of a crystal connected between OSC2 and OSC2BUF. PAL subcarrier frequency can be derived from this 4fSC clock. Ground if unused. Oscillator 2 Buffer. If a crystal is used, one pin is connected to OSC2, the other to OSC2BUF. Float this pin if unused. VGA Horizontal Sync Input. Active HIGH or active LOW polarity is sensed. VGA Vertical Sync Input. Active HIGH or active LOW polarity is sensed. Internal CPU enable. INTCPUEN enables the internal CPU when high. Field, Line and Pixel Reset. Resets video encoder engine to the start location on the outgoing frame. Used for genlock. Active high. Reset. Resets internal state machines and initializes default register values. Active high.
Global Controls INTCPUEN 59/77 FLP_RST 403 only RESET x/35
TTL input TTL input
30/37
TTL input
A/D Converter Interface R_IN, G_IN, 36/45, 39/48, 700 or 1000 Analog red, blue and green inputs. AC coupled RGB B_IN 44/53 mV video input signals. Nominal voltage range is 0.7 or 1.0 Volt peak-to-peak (selectable). Inputs are clamped to ground when HS_IN is active. VADCREF 42/51 700 or 1000 A/D Converter Top Reference Voltage Input. Input to mV voltage follower that supplies current to A/D converter reference resistors. Range is 0.5 - 2.0 volts. VTOUT 41/50 700 or 1000 A/D Converter Top Reference Voltage Output. Output of mV the internal VT buffer and direct connection to the A/D reference resistor ladder. If an external A/D voltage is used, it must be capable of driving the 100 load of the ladder. If the internal reference is used, it must be connected to an external 0.1 F de-coupling capacitor. VGACLKIN 53/67 TTL input A/D VGA converter clock input. Analog-to-digital converter external clock input if EXTVGASEL\ = L. EXTVGASEL\ 52/66 TTL input A/D VGA clock select. Selects the A/D clock source: EXTVGASEL\ = H: internal phase-locked loop; EXTVGASEL\ = L: external clock applied to VGACLKIN.
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JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
Pin Name VGACLKDIV 403 only CLAMP_REF
Pin Number
FS401/FS403
Type/Value LVTTL output LVTTL output
Pin Function Description A/D clock divided by N. VGACLKIN divided by N for connection to external phase-locked loop controller. Polarity selectable. VGA clock reference output. Clamp output signal. CLAMP_REF = H, when the internal clamp is active during the horizontal sync period, HS_IN. CLAMP_REF can be used for a reference input for an external PLL. Polarity selectable. Analog/Digital RGB in select. LOW selects internal A/D converters; HIGH selects external digital R7-0G7-0B7-0 inputs. If LOW, B7-0 become general purpose outputs. This pin has an internal pull-down and should be left open if the internal A/D is desired. Digital red inputs. Top 5 bits of 8-bit red input data. No connection if not used. Digital red input/OSD enable. Bit 2 of red input data if EXADSEL is high. Else, OSD enable pin (high enabled). No connection if not used. Digital red input/TV_HSYNC. Bit 1 of red input data if EXADSEL is high. Else, digital horizontal sync for YUV, RGB/SCART, and progressive video outputs. No connection if not used. Digital red input/TV_VSYNC. Bit 0 of red input data if EXADSEL is high. Else, digital vertical sync for YUV, RGB/SCART, and progressive video outputs. No connection if not used. Digital green input/OSD half tone. Bit 7 of green input data if EXADSEL is high. Else, OSD half tone input pin. No connection if not used. Digital green input/OSD red. Bit 4 of green input data if EXADSEL is high. Else, OSD red input pin. No connection if not used. Digital green input/OSD green. Bit 5 of green input data if EXADSEL is high. Else, OSD green input pin. No connection if not used. Digital green input/OSD blue. Bit 6 of green input data if EXADSEL is high. Else, OSD blue input pin. No connection if not used. Digital green input. Bottom 4 bits of 8-bit green input data. No connection if not used. Digital blue input. 8-bit blue input data if EXADSEL is high. GPO if not used (see GPO pin definition below). No connection if not used. General Purpose Outputs. 2 (FS401) or 8 bits (FS403) of general purpose outputs set by SIO commands to the GPO register. No connection if not used.
x/65
46/55
EXADSEL 403 only
x/23
TTL input
Digital RGB Inputs or OSD/GPO Pins R7-3 x/59-56, x/41 TTL input 403 only R2/OSDEN x/40 TTL input 403 only R1/ TV_HSYNC 403 only R0/ TV_VSYNC 403 only G7/OSDHT 403 only G4/OSDR 403 only G5/OSDG 403 only G6/OSDB 403 only G3-0 403 only B7-0 403 only GPO7-1 x/39 TTL input/ LVTTL output TTL input/ LVTTL output TTL input
x/38
x/27
x/26
TTL input
x/25
TTL input
x/24
TTL input
x/70-73 x/102-105, x/120-123
TTL input TTL input
GPO0
x/102, LVTTL 81/103, output x/104, x/105, x/120, x/121, x/122 96/123 LVTTL output
General Purpose Output 0. When the internal CPU is enabled, this bit signals when the frequency of the VGA input is high or low. Otherwise, it is a normal GPO bit. 13
COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
JANUARY 24, 2007
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
Pin Name
Pin Number
FS401/FS403
Type/Value LVTTL output analog video
Pin Function Description OSD clock. Output clock to external microprocessor to synchronize OSD data. Video output. As programmed by Command Register OFMT1-0 bits: 00 Luminance component Y of S-video. 01 Red component of RGB. 1X V component of YUV Video output. As programmed by Command Register OFMT1-0 bits: 00 Composite video. 01 Green component of RGB. 1X Y component of YUV. Video output. As programmed by Command Register OFMT1-0 bits: 00 Chrominance component of S-video. 01 Blue component of RGB. 1X U component of YUV. Composite sync output. Digital composite sync for YUV and RGB/SCART video outputs. High impedance (tri-state) when powered down. Horizontal sync output. Digital horizontal sync for YUV, RGB/SCART, and progressive video outputs. High impedance (tri-state) when powered down. Note: multiplexed with R1 on FS403 (see above). Vertical sync output. Digital horizontal sync for YUV, RGB/SCART, and progressive video outputs. High impedance (tri-state) when powered down. Note: multiplexed with R0 on FS403 (see above). Voltage reference input/output. If unconnected, except for a 0.1F capacitor to VDDDA for noise decoupling, the internal 1.235 Volt band-gap reference will be supplied to the three D/A Converters. An external 1.235 volt reference connected to CCOMP will override the internal voltage reference. Current Reference. A resistor between IREF and VSSDA sets the current range of the D/A converters. Use 392 for a 37.5 load and 787 for a 75 load. Bypass Capacitor. A 0.1F capacitor must be connected between CBYPASS and VDDDA to reduce noise at the D/A outputs.
OSDCLK x/19 403 only Video Outputs Y/R/V 12/11
CVBS/G/Y
15/14
analog video
C/B/U
17/16
analog video
CSYNC
20/20
LVTTL output LVTTL output
TV_HSYNC
32/39
TV_VSYNC
31/38
LVTTL output
D/A Voltage Reference CCOMP 8/7
+1.235 V
IREF
9/8
392/787 0.1 F
CBYPASS
11/10
14
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
Pin Name
Pin Number
FS401/FS403
Type/Value
Pin Function Description
Frame Buffer Port D15-0 79-76,73-62/
100-97,9491,88-81
A11-0 RAS\ CAS\ WE\ DQM
94-83/ 118-107 60/78 61/79 58/76 57/75
TTL input/ LVTTL output LVTTL output LVTTL output LVTTL output LVTTL output LVTTL output
Data port, frame store memory. 16-bit data bus for 16Mb SDRAM. Address port, frame store memory. 12-bit address bus for 16Mb SDRAM. Row address strobe. RAS\ output for 16Mb SDRAM frame store memory. Column address strobe. CAS\ output for 16Mb SDRAM frame store memory. Write enable. WE\ output for 16Mb SDRAM frame store memory. Data Qualify. Qualify data for 16Mb SDRAM frame store read/write operations. State is set by the memory access mode: DQM = L, enables memory outputs for read operations and exposes memory inputs for write operations; DQM = H, disables memory outputs and masks memory inputs Frame store clock input. Frame store input clock to be routed to RAMCK_OUT if RAMCK_SEL\ = L. Frame store clock select. Selects either internal or external clock for 16Mb SDRAM frame store memory. If RAMCK_SEL\ = H, the internal clock synthesized from OSC1 is selected. With RAMCK_SEL\ = L, the RAMCK_IN input is selected. Frame store clock output. RAMCK_OUT for 16Mb SDRAM frame store memory. Serial address length select. Selects the length of the serial address: SIOA10/7 = H: 10-bits SIOA10/7 = L: 7-bits Serial data address bit 0. . Selects the serial bus address: SIOA0 = H: 0x6A, 276 SIOA0 = L: 0x4A, 224 Serial data. Data line of the serial port. Serial clock. Clock line of the serial port. D/A Converter Power. A/D Converter Power. A/D Sample Clock Phase Lock Loop Power. Frame Store Clock Phase Lock Loop Power. Digital Power. 3.3 volt power for memory interface.
RAMCK_IN
100/127
TTL input TTL input
RAMCK_SEL\ 98/125
RAMCK_OUT 99/126 Serial Port SIOA10/7
LVTTL output TTL input
25/31
SIOA0
26/32
TTL input
SIODATA 24/30 TTL input SIOCLK 23/29 TTL input Power and Ground VDDDA 10, 13, 16, 18/ +3.3 V VDDAD VDDPA VDDPF VDD
9, 12, 15, 17 33, 37, 38, 45/ 42, 46, 47, 54 47/60 1/128
+3.3 V +3.3 V +3.3 V +3.3 V
VSSDA
19, 27, 54, 74, 82, 95/ 18, 33, 68, 80, 90, 95, 106, 119 7, 14/6, 13
0V
D/A Converter Ground. 15
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COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
Pin Name VSSAD VSSPA VSSPF VSS
Pin Number
FS401/FS403 34, 35, 40, 43/ 43, 44, 49, 52
Type/Value 0V 0V 0V 0V
Pin Function Description A/D Converter Ground. A/D Sample Clock Phase Lock Loop Ground. Frame Store Clock Phase Lock Loop Ground. Digital ground.
48/61 97/124
6, 21, 22, 28, 29, 51, 55, 56, 75, 80/ 5, 21, 22, 28, 34, 36, 64, 69, 74, 89, 96, 101
16
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4. Control Register Definitions
4.1 Control Register Functions
Control register functions are summarized in Table 3. Each internal register is up to 16-bits wide. To access a register two 8-bit data words must be transferred. In the case of a write, writing the second byte loads the internal 16-bit register. Most registers have type read/write. Read only registers access the internal status of the FS400. Write-only registers initiate the transfer of data. There are two methods for an external processor to control the FS400. The first is to directly program the FS400 SIO hardware registers. The external processor would sample continuously the IHC and IVC registers to monitor the size and speed of the input video. Additionally, it would read the SHV, EHV, SVV, and EVV to determine the size of the active area of the input image (input calibration). Lastly, the external processor would have to calculate the values for the ILS, VSC, IHS, IHA, HSC, OHO, and OVO registers. The second method is to allow the FS400's internal micro-controller to do most of the required work. The external processor writes to a set of high level registers (software registers) to direct the internal microcontroller's actions. The internal micro-controller takes care of all the real-time sampling and calculations for the lower level registers (hardware registers). When enabled, the internal micro-controller takes control of many of the hardware registers. These registers are GPO, ILS, VSC, IVO, IHS, IHA, HSC, IHO, CR, CRE, OHO, OVO, SHV, EHV, SVV, EVV, AVT, and FLK. The external processor should not write to these registers while the internal microcontroller is enabled. The internal micro-controller also provides high level registers (software registers). These registers are described in the following sections. The interface the software registers is identical to the hardware registers via the SIO. Additionally, the external processor is allowed to write to the following hardware registers: CON, BRT, SHP, and CSC.
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4.2 Internal Micro-Controller Programming
4.2.1 Input Calibration
The internal micro-controller needs to know what portion of the input video signal contains active video. Determining this information is referred to as Input Calibration. The input calibration information is used by the internal micro-controller to calculate the low-level registers that scale the input image to fit on the output device. The internal micro-controller stores the input calibration information as 4 ratios that describe the active video area in relation to the total input video signal. These 4 ratios are: SHV HAT SVV VAT (Number of pixel times from HSync to the start of the active video) / (The total pixel times from HSync to HSync) * 65536 (Number of active pixels) / (The total pixel times from HSync to HSync) * 65536 (Number of lines from VSync to the start of the active video) / (The total lines from VSync to VSync) * 65536 (Number of active lines) / (The total lines from VSync to VSync) * 65536
For example, if the input video signal has 1138 pixel times from HSync to HSync, only 1024 of the pixels are active, and the first active pixel is at pixel time 57, then SHV and HAT would be: SHV = 57 / 1138 * 65536 HAT = 1024 / 1138 * 65536 There are two methods of determining the input calibration: auto input calibration and manual input calibration. Additionally, the internal micro-controller can store the input calibration for 4 video modes. 4.2.1.1 Auto Input Calibration When the FS400 is in auto input calibration mode, then the internal micro-controller will use the active video registers (SHV, EHV, SVV, and EVV) to determine the input calibration. The internal microcontroller will sample the active video registers until their values stabilize for at least 600 milliseconds. The internal micro-controller will wait up to 3 seconds for the active video registers to stabilize. If the active video register do not stabilize, the internal micro-controller will revert to the default input calibration information to display the image. Additionally, if the input calibration values calculated from the active video registers are outside of the minimums and maximums allowed, the internal micro-controller will revert to the default input calibration information. The internal micro-controller will continue to sample the active video registers. If the registers do stabilize at a later time, the default input calibration will be replaced with the calculated input calibration. After the initial input calibration is acquired, the internal micro-controller continues to sample the active video registers. If the input calibration calculated from the new sample indicates a larger active video area, then the new input calibration is used. Auto input calibration is enabled by clearing the DSICAL bit in the SCR register. This is the default mode of operation. There is nothing else an external controller need to do to allow automatic calibration to work. However, an external controller can modify the behavior of auto input calibration by changing the following configuration values via the CCR and CDR registers. CCR_DEF_SHV CCR_MIN_SHV CCR_MAX_SHV CCR_DEF_HAT CCR_MIN_HAT
JANUARY 24, 2007
Default Start of Horizontal Video Minimum Start of Horizontal Video Maximum Start of Horizontal Video Default Horizontal Active Minimum Horizontal Active 18
COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
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PRODUCT SPECIFICATION REV. NO. 1.7
CCR_MAX_HAT CCR_DEF_SVV CCR_MIN_SVV CCR_MAX_SVV CCR_DEF_VAT CCR_MIN_VAT CCR_MAX_VAT
Maximum Horizontal Active Default Start of Vertical Video Minimum Start of Vertical Video Maximum Start of Vertical Video Default Vertical Active Minimum Vertical Active Maximum Vertical Active
An external controller can reset the input calibration and force the internal micro-controller to reacquire the input calibration information by setting the RSTICAL bit in the SCR register. 4.2.1.2 Manual Input Calibration The auto input calibration can be by-passed by setting the DSICAL bit in the SCR register. When DSICAL is set, the internal micro-controller will use the manual input calibration values. An external controller can modify the manual input calibration values by changing the following configuration values via the CCR and CDR registers: CCR_SHV Start of Horizontal Video CCR_HAT Horizontal Active CCR_SVV Start of Vertical Video CCR_VAT Vertical Active The external controller must set the MICALNEW bit in the SCR register after each change to the manual input calibration values. The internal controller will not recognize a change in the state of DSICAL until the next video mode change or until the RSTICAL bit in the SCR register is set. The manual input calibration values do not change when a new video mode is detected, except when Input Calibration Tables are enabled. If an external processor needs to write different manual input calibration information for new video modes, it must poll the MCC bit in the SSR register to determine when a new video mode is present. Next, the external processor can read the CCR_IVC and CCR_IHC configuration values to determine the new video mode and then write the appropriate input calibration information. The auto input calibration can be by-passed by setting the DSICAL bit in the SCR register. When DSICAL is set, the internal micro-controller will use the manual input calibration values. An external controller can modify the manual input calibration values by changing the following configuration values via the CCR and CDR registers. CCR_SHV CCR_HAT CCR_SVV CCR_VAT Start of Horizontal Video Horizontal Active Start of Vertical Video Vertical Active
The external controller must set the MICALNEW bit in the SCR register after each change to the manual input calibration values. The internal controller will not recognize a change in the state of DSICAL until the next video mode change or until the RSTICAL bit in the SCR register is set. The manual input calibration values do not change when a new video mode is detected, except when Input Calibration Tables are enabled. If an external processor needs to write different manual input calibration information for new video modes, it must poll the MCC bit in the SSR register to determine when a new video mode is present. Next, the external processor can read the CCR_IVC and CCR_IHC configuration values to determine the new video mode and then write the appropriate input calibration information.
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PRODUCT SPECIFICATION REV. NO. 1.7
4.2.1.3 Input Calibration Tables The internal micro-controller can store input calibration information for four video modes when in both manual and auto input calibration mode. Setting the ENICTBL bit in the SCR register enables this feature. During a video mode change, the internal micro-controller will save the accumulated input calibration of the last video mode and its IVC and IHC values into the input calibration table. Next, the internal microcontroller will search the table entries for an entry that match the IHC and IVC of the new mode. If a match is found, then the input calibration information is retrieved from the table. Setting the RSTICAL bit in the SCR register will clear the table entry for the current mode. The input calibration table can be read and modified by accessing the following configuration values via the CCR and CDR registers. CCR_ICAL_TABLE_x_IVC CCR_ICAL_TABLE_x_IHC CCR_ICAL_TABLE_x_HAT CCR_ICAL_TABLE_x_SHV CCR_ICAL_TABLE_x_VAT CCR_ICAL_TABLE_x_SVV x = 0, 1, 2, or 3
4.2.2 Output Calibration
The internal micro-controller needs to know the location of the first displayable pixel and line and how many pixels and lines the output device can display. This information is referred to as the Output Calibration. The internal micro-controller has built-in default output calibration that works well for supported output devices. However, an external controller can change the output calibration to suit a specific output device. The starting pixel and starting line locations are stored in HOHOS and HOVOS. The external controller may read and write these registers at any time. Any changes will take effect upon the next output frame. The number of pixels and lines that can be displayed are stored in the TVP (TV Pixels) and TVL (TV Lines) registers. The external controller may read and write these registers at any time. Any changes will take effect after the internal controller recalculates the low level registers. Additionally, the FS400 is capable of display a 75% color bar pattern to assist the user in manually adjusting the output calibration. Setting the OCAL bit in the SCR register enables the 75% color bar pattern. Any change to TV_CLK, PROG_INT, or PAL_NTSC fields of the HCRS register causes the internal micro-controller to initialize the HOHOS, HOVOS, TVL, and TVP registers to defaults appropriate to the new output mode.
4.2.3 Zoom
There are two zooming methods. The first is to set the ZOOM bit in the HCRES register for 2x-zoom. The second is to use the HSS (Horizontal Scale Step) and the VSS (Vertical Scale Step) registers for variable zoom. Setting the ZOOM bit in the HCRES register causes the pixels to double in size. The HPP (Horizontal Pan Position) and the VPP (Vertical Pan Position) are used to pan the zoomed image. 20
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
The pixels double in size in the vertical direction. The internal micro-controller also attempts to double pixels in the horizontal direction. This is possible for most video modes; however, with very large input images and very small output devices the pixels will be scaled to something less than 2x horizontally. The HSS (Horizontal Scale Step) and the VSS (Vertical Scale Step) registers can be used to scale the image up or down (larger or smaller). This method allows for a variable zoom that works independently in the horizontal and vertical directions. The HPO (Horizontal Position Offset) and the VPO (Vertical Position Offset) are used to pan the variable zoomed image. The ZOOM bit and the HSS and VSS register pair effects are mutually exclusive. They do not compound each other. The ZOOM bit is the highest priority. If the ZOOM bit is set, then the image is in the 2x-zoom mode, regardless of the state of HSS and VSS. When the ZOOM bit is cleared, HSS and VSS control the zoom effect. The minimum and maximum values of HSS and VSS vary depending upon the size of the input image and the size of the output device. The internal micro-controller checks the limits of these registers each time they change. If the values in the HSS and VSS registers are out of range, the internal microcontroller will overwrite the register with either the minimum value or the maximum value. However, it can take up to 25ms before the internal micro-controller does this. Therefore, an external controller should not read HSS or VSS until 25ms after writing to one of these registers.
4.2.4 Panning
When the ZOOM bit in the HCRES register is cleared HPO (Horizontal Position Offset) and VPO (Vertical Position Offset) control panning. HPP (Horizontal Pan Position) and VPP (Vertical Pan Position) control panning when the ZOOM bit in the HCRES register is set. The HPP and HPO values are expressed as a signed ratio of the horizontal total * 32768. The VPP and VPO values are expressed as a signed ratio of the vertical total * 32768. These signed ratios are added to the start of active video ratios (SHV and SVV) to compute a new start of active video. The CCR_HPO_STEP and CCR_VPO_STEP configuration values contain the percentage of the horizontal and vertical totals that represent one pixel. The processor can read CCR_HPO_STEP and add or subtract the value from HPO or HPP to move the image one pixel horizontally. The CCR_VPO_STEP value is added or subtracted from the VPO and VPP to move the image one pixel vertically. The minimum and maximum values of HPO, VPO, HPP and VPP vary depending upon the size of the input image. The internal micro-controller checks the limits of these values each time they change. If the values in the HPO, VPO, HPP and VPP registers are out of range, the internal micro-controller will overwrite the register with either the minimum value or the maximum value. However, it can take up to 25ms before the internal micro-controller does this. Therefore, an external controller should not read HPO, VPO, HPP or VPP until 25ms after writing to one of these registers.
4.2.5 Picture Control
The following registers control the picture quality. CON BRT SHP CSC Contrast Coefficient Brightness Coefficient Sharpness Coefficient Color Saturation Coefficient
CON, BRT, SHP, and CSC are low level hardware registers. However, the internal micro-controller does not modify the contents of these registers. An external controller is free to modify them as needed. Additionally, there are several bits in the control registers that are used to control picture quality. 21
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PRODUCT SPECIFICATION REV. NO. 1.7
In the HCRS register: LNTCH CBP PEDSTL In the HCRES register: RGBGAIN FREEZE In the SCR register SFLK Flicker Filter 1x or 1.43x RGB Input Gain Freeze the Input Image Luminance Notch Filter Chroma Bandpass Filter US NTSC Black Pedestal
4.2.6 Video Mode Changes
A video mode change starts when the internal micro-controller detects a significant change in either IVC (Input Vertical Count) or IHC (Input Horizontal Count). The internal micro-controller samples IVC and IHC approximately every 50ms. When a change is detected and is stable for several sample periods, the mode change process is started and the MCS (Mode Change Start) bit is set in the SSR register. Additionally, a mode change is initiated when the RSTVMODE bit is set in the SCR register or when the OCAL bit in the SCR register is cleared. If the input calibration tables are enabled (ENICTBL bit in the SCR register is set), then the accumulated input calibration for the old video mode is stored in the input calibration table. Next, the input calibration table is searched for an entry that matches the IVC and IHC of the new mode. If one is found, then the input calibration is retrieved from the table. If manual input calibration is enabled (DSICAL bit in SCR register is set) and the no input calibration information was found in the input calibration table, then the input calibration information is retrieved from the manual input calibration configuration values. If auto input calibration is enabled (DSICAL bit in SCR register is clear) and the no input calibration information was found in the input calibration table, then the internal micro-controller begins sampling of the active video registers (SHV, EHV, SVV, and EVV). Once the input calibration information is obtained, the internal micro-controller calculates the values for the low-level hardware registers and programs them. At this point the MCS bit in the SSR is cleared and the MCC (Mode Change Complete) bit in the SSR is set. A video mode change does not change the state of any other software registers. This includes the FREEZE and ZOOM bits in the HCRES register and the HPO, VPO, HPP, VPP, HSS, and VSS registers. If the external controller modifies any of these, it might be desirable for the external controller to return them to there reset state after a video mode change is complete. An external controller can detect a video mode change by polling the MCC bit in the SSR. The MCC bit remains set until an external controller sets the CLRMCC bit in the SCR register. The recommended polling frequency is at least once per second, but not more than 20 times per second.
4.2.7 By-passing the Internal Micro-Controller
When the FS400's built-in microprocessor is enabled, it is responsible for programming the following lowlevel hardware registers: IHO IVO Input Horizontal Offset Input Vertical Offset 22
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
IHA IHS OHO OVO VSC CR CRE HSC FLK AVT
Input Horizontal Active Input Horizontal Samples Output Horizontal Offset Output Vertical Offset Vertical Scaling Coefficient Control Register Control Register Extended Horizontal Scaling Coefficient Flicker Filter Active Video Threshold
The internal micro-controller also accesses the following read-only low-level hardware registers: IVC IHC SHV EHV SVV EVV Input Vertical Count Input Horizontal Count Start Horizontal Video End Horizontal Video Start Vertical Video End Vertical Video
When the internal micro-controller is enabled, an external controller should only access the following registers: SCR SSR HCRS HCRES HPO VPO HSS VSS HPP VPP TVP TVL CCR CDR HOHOS HOVOS CON BRT SHP CSC Software Control Register Software Status Register Hardware Control Register Shadow Hardware Control Register Extended Shadow Horizontal Position Offset Vertical Position Offset Horizontal Scale Step Vertical Scale Step Horizontal Pan Position Vertical Pan Position TV Pixels TV Lines Configuration Command Register Configuration Data Register Hardware Output Horizontal Offset Shadow Hardware Output Vertical Offset Shadow Contrast Coefficient Brightness Coefficient Sharpness Coefficient Color Saturation Coefficient
An external controller can disable the internal micro-controller by clearing the ENABLE bit in the SCR register. When disabled (either through software or using the INTCPUEN pin), the internal microcontroller will no longer access any of the FS400 registers. The external controller becomes responsible for programming all of the low-level hardware registers. The internal micro-controller will only respond to the RESET and ENABLE bits in the SCR register while it is disabled. Changes to any of the other software registers (SCR, HCRS, HCRES, HPO, VPO, HSS, VSS, HPP, VPP, TVP, TVL, CCR, CDR, HOHOS, HOVOS) will have no effect until the internal microcontroller is re-enabled. The micro controller can be re-enabled by setting the ENABLE bit in the SCR register. The internal micro-controller will begin processing at the same point that it was disabled at. Any changes to the software registers will be processed. The low-level hardware register will eventually be re-programmed.
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PRODUCT SPECIFICATION REV. NO. 1.7
It is also possible to disable two portions of the internal micro-controllers program code. These are the video mode detect and the auto input calibration program code. The video mode detect program code is disabled by setting the DSVMDET bit in the SCR register. The video mode detect code usually samples the IHC and IVC registers looking for a stable change to indicate a new video mode. When this code is disabled, no new video modes will be detected. An external processor could sample IHC and IVC or use another method to determine a video mode change. The external processor would then have to program the CCR_IHC and the CCR_IVC configuration values via the CCR and CDR and then set the RSTVMODE bit in the SCR to force a video mode update. The video mode detect code can be re-enabled at any time by clearing the DSVMET bit in the SCR register. Setting the DSICAL bit in the SCR register disables the input calibration program code. This referred to as manual input calibration mode and is discussed in section 4.2.1.2 above.
4.2.8 Special Internal Micro-Controller SIO Requirements
The interface to the internal micro-controller's software registers is identical to the hardware registers via the SIO. However, the internal micro-controller is not able to process code while an external processor is accessing the SIO. Therefore, repeated back to back SIO access can starve the internal micro-controller of processing time. This is not a concern for short bursts of back to back SIO accesses, but long loops of repeated polling of an SIO register should be avoided. If it is necessary to repeatedly poll a register via the SIO, it is recommended that there be a delay of about 1 to 5 millisecond between SIO accesses. This will allow the internal micro-controller to continue it's processing in a timely manor. One example of the need to repeated poll an SIO register is when an external processor writes a CCR_READ command to the CCR register. The external processor must wait until the CCR register is set to CCR_COMPLETE (0) before it could read the data from the CDR. A programmer might be tempted to write a loop that continuously reads the CCR register until it is set to CCR_COMPLETE. This would slow down or even stop the processing in the internal micro-controller. To avoid this, add at least a 1 to 5ms delay into the loop to allow the internal micro-controller to continue processing.
4.3 Disabling the Internal Micro-Controller
To be added later.
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4.4 Control Register Definitions
Table 3. Control Register Map
Function Reg. Bit # Name Type Input Horizontal Offset 0 7-0 IHO7-0 R/W 1 2-0 IHO10-8 R/W Input Vertical Offset 2 7-0 IVO7-0 R/W 3 3-0 IVO11-8 R/W Input Horizontal Active Width 4 7-0 IHAW7-0 R/W 5 1-0 IHAW9-8 R/W Input Lines Stored 6 7-0 ILS7-0 R/W 7 1-0 ILS9-8 R/W Input Horizontal Samples (per line) 8 7-0 IHS7-0 R/W 9 2-0 IHS10-8 R/W Input Horizontal Count A 7-0 IHC7-0 R B 1-0 IHC9-8 R Input Vertical Count (lines) C 7-0 IVC7-0 R D 3-0 IVC11-8 R Vertical Scaling Coefficient E 7-0 VSC7-0 R/W F R/W Command Register 10 7-0 CR7-0 R/W 11 5-0 CR13-8 R/W Status Register 12 7-0 SR7-0 R 13 7-0 SR15-8 R Command Register Extended 14 7-0 CRE7-0 R/W 15 3-0 CRE11-8 R/W Start Horizontal Active VGA 16 7-0 SHV7-0 R 17 2-0 SHV10-8 R End Horizontal Active VGA 18 7-0 EHV7-0 R 19 2-0 EHV10-8 R Start Vertical Active VGA 1A 7-0 SVV7-0 R 1B 2-0 SVV10-8 R End Vertical Active VGA 1C 7-0 EVV7-0 R 1D 2-0 EVV10-8 R Active Video Threshold 1E 7-0 AVT7-0 R/W 1F R/W
JANUARY 24, 2007
Reset Value 80 (128.) 00 05 00 00 (512.) 02 DC (220.) 00 FE (766.) 02
00 00 00 00 00 02 00 (256.) 01
00 00 25
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FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
Function Reg. Bit # Name Type Output Horizontal Offset 20 7-0 OHO7-0 R/W 21 1-0 OHO9-8 R/W Output Vertical Offset 22 7-0 OVO7-0 R/W 23 1-0 OVO9-8 R/W Horizontal Scaling Coefficient 24 7-0 HSC7-0 R/W 25 0 HSC8 R/W Contrast Coefficient 26 5-0 CON5-0 R/W 27 Brightness Coefficient 28 7-0 BRT7-0 R/W 29 Sharpness Coefficient 2A 4-0 SHP4-0 R/W 2B Flicker Filter Coefficient 2C 4-0 FLK4-0 R/W 2D Color Saturation Coefficient 2E 5-0 CSC5-0 R/W 2F General Purpose Outputs 34 7-0 GPO7-0 R/W 35 Software Control Register 60 7-0 SCR7-0 R/W 61 7-0 SCR15-8 R/W Software Status Register 62 7-0 SSR7-0 R 63 7-0 SSR15-8 R Hardware Control Register Shadow 64 7-0 HCRS7-0 R/W 65 7-0 HCRS15-8 R/W Hardware Control Register Extended Shadow 66 7-0 HCRES7-0 R/W 67 7-0 HCRES15- R/W
8
Reset Value C0 (192.) 00 20 (32.) 00 00 00 20 (32.) 00 00 00 00 00 00 00 20 (32.) 00 00 00 02 (33794.) 84
80 (128.) 00 20 (800.) 03
Horizontal Position Offset 68 7-0 HPO7-0 69 7-0 HPO15-8 Vertical Position Offset 6A 7-0 VPO7-0 6B 7-0 VPO15-8 Horizontal Scale Step 6C 7-0 HSS7-0 6D 7-0 HSS16-8 Vertical Scale Step 6E 7-0 VSS7-0 6F 7-0 VSS15-8
JANUARY 24, 2007
R/W R/W R/W R/W R/W R/W R/W R/W
00 00 00 00 00 00 00 00 26
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FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
Function Reg. Bit # Name Type Horizontal Pan Position 70 7-0 HPP7-0 R/W 71 7-0 HPP15-8 R/W Vertical Pan Position 72 7-0 VPP7-0 R/W 73 7-0 VPP15-8 R/W TV Pixels 74 7-0 TVP7-0 R/W 75 7-0 TVP15-8 R/W TV Lines 76 7-0 TVL7-0 R/W 77 7-0 TVL15-8 R/W Configuration Command Register 78 7-0 CCR7-0 R/W 79 7-0 CCR15-8 R/W Configuration Data Register 7A 7-0 CDR7-0 R/W 7B 7-0 CDR15-8 R/W Hardware Output Horizontal Offset Shadow 7C 7-0 HOHOS7-0 R/W 7D 7-0 HOHOS15-8 R/W Hardware Output Vertical Offset Shadow 7E 7-0 HOVOS7-0 R/W 7F 7-0 HOVOS15-8 R/W
Reset Value 00 00 00 00 92 (658.) 02 9C (412.) 01 00 00 00 00 B2 (178.) 00 26 (38.) 00
Following reset at power-up, the status of the internal registers is as indicated under "Reset Value" above. Note set all unused bits are set to zero and all unused register bits are set to zero for readback.
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FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5 Control Registers Definitions
In the following definitions, range is defined as: {min value : [max value]}
4.5.1 IHO - Input Horizontal Offset Input Horizontal Offset Low (0)
7 IHO7 6 IHO6 5 IHO5 4 IHO4 3 IHO3 2 IHO2 1 IHO1 0 IHO0
Input Horizontal Offset High (1)
7 0 6 0 5 0 4 0 3 0 2 IHO10 1 IHO9 0 IHO8
Register 1, 0
Bit# 2-0, 7-0
Bit Name IHO10-0
Description Input horizontal offset bits [10-0]. Horizontal displacement of the image in pixels from the leading edge of horizontal sync. Programming a value greater than IHS is illegal, preventing any pixels from being written into the Frame Store.
Range: {0 : [IHS-1]}
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FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.2 IVO - Input Vertical Offset Input Vertical Offset Low (2)
7 IVO7 6 IVO6 5 IVO5 4 IVO4 3 IVO3 2 IVO2 1 IVO1 0 IVO0
Input Vertical Offset High (3)
7 0 6 0 5 0 4 0 3 IVO11 2 IVO10 1 IVO9 0 IVO8
Register 3, 2
Bit# 3-0, 7-0
Bit Name IVO11-0
Description Input vertical offset bits [11:0]. Vertical displacement of the image in lines from the leading edge of vertical sync plus a one line bias.
Range: {0 : [IVC - 1]}
Note: Input Vertical Count (IVC) must be read to obtain the register value.
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FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.3 IHAW - Horizontal Active Width Horizontal Active Width Low (4)
7 IHAW7 6 IHAW6 5 IHAW5 4 IHAW4 3 IHAW3 2 IHAW2 1 IHAW1 0 IHAW0
Horizontal Active Width High (5)
7 0 6 0 5 0 4 0 3 0 2 0 1 IHAW9 0 IHAW8
Register 5, 4
Bit# 1-0, 7-0
Bit Name IHAW9-0
Description Horizontal active width [9:0]. Number of incoming pixels to be stored in the Frame Store Memory following extraction from the incoming active video area.
Range: {0 : [1023] }
Note: IHAW optimizes the number of stored pixels. Line store capacity limits the maximum value of IHAW to 1023 active pixels per video line
Restrictions: 1. IHAW < IHS-1 2. NTSC:
HSC IHAW * 1 + + OHO < 894 64
3. Zoom NTSC:
HSC 2 * IHAW * 1 + + OHO < 894 64
4. PAL:
HSC IHAW * 1 + + OHO < 1125 64
5. Zoom PAL:
HSC 2 * IHAW * 1 + + OHO < 1125 64
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FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.4 ILS - Input Lines Stored Input Lines Stored Low (6)
7 ILS7 6 ILS6 5 ILS5 4 ILS4 3 ILS3 2 ILS2 1 ILS1 0 ILS0
Input Lines Stored High (7)
7 0 6 0 5 0 4 0 3 0 2 0 1 ILS9 0 ILS8
Register 7, 6
Bit# 1-0, 7-0
Bit Name ILS9-0
Description Input lines stored bits [9:0]. Number of incoming lines per field to be stored in the Frame Store Memory following extraction from the incoming active video area.
Range: {0 : [(IVC - 1)]} Restrictions: 1. At all times:
IVC - 1 ILS < VSC 1- 64
2. NTSC : ILS + 2*OVO < 525 3. PAL: ILS + 2*OVO < 625
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PRODUCT SPECIFICATION REV. NO. 1.7
4.5.5 IHS - Input Horizontal Samples Input Horizontal Samples Low (8)
7 IHS7 6 IHS6 5 IHS5 4 IHS4 3 IHS3 2 IHS2 1 IHS1 0 IHS0
Input Horizontal Samples High (9)
7 0 6 0 5 0 4 0 3 0 2 IHS10 1 IHS9 0 IHS8
Register 9, 8
Bit# 2-0, 7-0
Name IHS10-0
Description Input horizontal line samples bits [10:0]. Terminal count of the number of clocks per horizontal line between incoming horizontal sync pulses. Internal ADCK phase-locked loop is programmed with this value.
Range: 16MHz IHS*Incoming Horizontal Line Frequency 50MHz
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PRODUCT SPECIFICATION REV. NO. 1.7
4.5.6 IHC - Input Horizontal Count Input Horizontal Count Low (A)
7 IHC7 6 IHC6 5 IHC5 4 IHC4 3 IHC3 2 IHC2 1 IHC1 0 IHC0
Input Horizontal Count High (B)
7 0 6 0 5 0 4 0 3 0 2 0 1 IHC9 0 IHC8
Register B, A
Bit# 1-0, 7-0
Bit Name IHC9-0
Description Input horizontal count bits [9:0] (read only). Number of 4fSC clock pulses per horizontal line. 4fSC is the selected OSC clock (17.734 MHz for PAL or 14.318 MHz for NTSC). IHC can be read to determine the incoming horizontal line frequency for auto selection of the incoming video format.
Range: {0:[1023]}
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FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.7 IVC - Input Vertical Count Input Vertical Count Low (C)
7 IVC7 6 IVC6 5 IVC5 4 IVC4 3 IVC3 2 IVC2 1 IVC1 0 IVC0
Input Vertical Count High (D)
7 0 6 0 5 0 4 0 3 IVC11 2 IVC10 1 IVC9 0 IVC8
Register D, C
Bit# 3-0, 7-0
Bit Name IVC11-0
Description Input vertical line count bits [11:0] (read only). Terminal count of the number of incoming lines per frame. IVC is used to determine the incoming vertical refresh frequency for auto selection of the incoming video format.
Range: {0:[4095]}
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FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.8 VSC - Vertical Scaling Coefficient Vertical Scaling Coefficient (E)
7 VSC7 6 VSC6 5 VSC5 4 VSC4 3 VSC3 2 VSC2 1 VSC1 0 VSC0
Vertical Scaling Coefficient (F)
7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Register E
Bit# 7-0
Bit Name VSC7-0
Description Vertical scaling coefficient bits [7:0], m. Vertical scaling factor = (1 - m/ 256). m is the line reduction number modulo 256 due to vertical filtering. Load. Writing to register F activates register E data.
F
-
-
Range: {0:[192]} Restrictions: 1. At all times:
1 IVC - 1 ILS < * 2 1 - VSC 64
2. NTSC : ILS + OVO < 259 3. PAL: ILS + OVO < 310 Example: 480 line VGA image mapped to 400 line image. VSC = (1-(400/480))*256 = 42.667 Use 42 for the Coefficient value
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FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.9 CR - Command Register Command Register Low (10)
7 PEDSTL 6 CBP 5 LNTCH 4 YCOFF 3 COMPOFF 2 ADCOFF 1 CLKOFF 0 RESET
Command Register High(11)
7 0 Reg 10 10 10 10 10 10 10 10 11 Bit# 0 1 2 3 4 5 6 7 3-0 6 0 5 OFMT1 Bit Name RESET CLKOFF ADCOFF COMPOFF YCOFF LNTCH CBP PEDSTL TV_CLK1-0 4 OFMT0 3 2 PAL_NTSC PROG_INT 1 TV_CLK1 0 TV_CLK0
11 11 11
2 3 5-4
PROG_INT PAL_NTSC OFMT1-0
Description 0: run 1: reset video pipeline (control registers are not affected) 0: FS400 clocks powered on. 1: FS400 clocks powered off. 0: A/D converter powered on. 1: A/D converter powered off. 0: Composite D/A converter powered on. 1: Composite D/A converter powered off. 0: Y/C & Chroma D/A converter powered on. 1: Y/C & Chroma D/A converter powered off. 0: Bypass luminance notch filter. 1: Insert luminance notch filter. 0: Bypass chroma bandpass filter. 1: Insert chroma bandpass filter. 0: Bypass pedestal 1: Insert US NTSC black pedestal TV Clock Select 00 = 4FSC crystal or oscillator 01 = non-subcarrier crystal or oscillator 10 = 8FSC crystal or oscillator 0 = Interlaced Output 1 = Progressive Output 0 = NTSC 1 = PAL Output Format 00 = Y/C and Composite Video 01 = RGB 1x = YUV
Typical Output Mode Settings: TV Mode NTSC PAL VGA SVGA 100Hz PAL Progressive NTSC (720x480) Super NTSC (1280x480) Super PAL (1280x575)
TV_CLK 0 0 2 2 1 1 2 2
PROG_INT 0 0 1 1 0 1 0 0
PAL_NTSC 0 1 0 1 1 0 0 1
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JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.10 SR - Status Register Status Register Low (12)
7 0 6 0 5 0 4 0 3 REVID3 2 REVID2 1 REVID1 0 REVID0
Status Register High (13)
7 0 6 0 5 0 4 0 3 0 2 0 1 1 0 0
Register 12
Bit# 3-0
Bit Name REVID3-0 FAMILY6-0
Description Chip revision identification. Starts at 0. Revision History: April 1999 - Revision 0 Family ID. Indicates the product family for chip identification.
13
6-0
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JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.11 CRE - Command Register Extended Command Register Extended Low (14)
7 0 6 0 5
VGAINTDET
4
VGAREFPOL
3
VGACLKPOL
2 FREEZE
1 RGBGAIN
0 ZOOM
Command Register Extended High (15)
7 EVVCLR 6 SVVCLR 5 EHVCLR 4 SHVCLR 3 BIPTALL 2 BIPGEN2 1 BIPGEN1 0 BIPGEN0
Register 14 14
Bit# 5 4
Bit Name
Description
VGAINTDET 0: Ignore interlaced input
VGAREFPOL
(read only) 14 3
VGACLKPOL
1: Detect interlaced input 0 = VGA syncs reference polarity rising edge 1 = VGA syncs reference polarity falling edge 0 = VGA clock reference polarity rising edge 1 = VGA clock reference polarity falling edge 0: Continuous update 1: Freeze frame 0: 1x input gain 1: 1.43 input gain 0: Zoom off 1: Zoom on 0: run 1: clear EVV and re-detect 0: run 1: clear SVV and re-detect 0: run 1: clear EHV and re-detect 0: run 1: clear SHV and re-detect 0: Normal BIPGEN image size (512x512) 1: Tall BIPGEN image size (512x1024) Built-in Pattern Generator: 000 = Disabled 001 = All Waveforms 010 = 100% Color Bars 011 = 75% Color Bars 100 = Cross Hatch 101 = Red Gradient 110 = Green Gradient 111 = Blue Gradient
(read only) 14 14 14 15 15 15 15 15 15 2 1 0 7 6 5 4 3 2-0 FREEZE RGBGAIN ZOOM EVVCLR SVVCLR EHVCLR SHVCLR BIPTALL BIPGEN2-0
Notes: When ZOOM = 1, FLK and SHP registers are disabled, and IHAW should be reduced by 1/2. 38
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.12 Start Horizontal Active VGA Start Horizontal Active VGA Low (16)
7 SHV7 6 SHV6 5 SHV5 4 SHV4 3 SHV3 2 SHV2 1 SHV1 0 SHV0
Start Horizontal Active VGA High (17)
7 0 6 0 5 0 4 0 3 0 2 SHV10 1 SHV9 0 SHV8
Register 17, 16
Bit# 2-0, 7-0
Bit Name SHV10-0
Description Start Horizontal Active VGA bits [10:0] (read only). Number of 4fSC clocks from the start of a line to the first detected active video.
Range: {0:[2047]}
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JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.13 End Horizontal Active VGA End Horizontal Active VGA Low (18)
7 EHV7 6 EHV6 5 EHV5 4 EHV4 3 EHV3 2 EHV2 1 EHV1 0 EHV0
End Horizontal Active VGA High (19)
7 0 6 0 5 0 4 0 3 0 2 EHV10 1 EHV9 0 EHV8
Register 19, 18
Bit# 2-0, 7-0
Bit Name EHV10-0
Description End Horizontal Active VGA bits [10:0] (read only). Number of 4fSC clocks from the start of a line to the last detected active video.
Range: {0:[2047]}
40
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.14 Start Vertical Active VGA Start Vertical Active VGA Low (1A)
7 SVV7 6 SVV6 5 SVV5 4 SVV4 3 SVV3 2 SVV2 1 SVV1 0 SVV0
Start Vertical Active VGA High (1B)
7 0 6 0 5 0 4 0 3 0 2 SVV10 1 SVV9 0 SVV8
Register 1B, 1A
Bit# 2-0, 7-0
Bit Name SVV10-0
Description Start Vertical Active VGA bits [10:0] (read only). Number of 4fSC clocks from the start of a frame to the first detected active video.
Range: {0:[2047]}
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FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.15 End Vertical Active VGA End Vertical Active VGA Low (1C)
7 EVV7 6 EVV6 5 EVV5 4 EVV4 3 EVV3 2 EVV2 1 EVV1 0 EVV0
End Vertical Active VGA High (1D)
7 0 6 0 5 0 4 0 3 0 2 EVV10 1 EVV9 0 EVV8
Register 1D, 1C
Bit# 2-0, 7-0
Bit Name EVV10-0
Description End Vertical Active VGA bits [10:0] (read only). Number of 4fSC clocks from the start of a frame to the last detected active video.
Range: {0:[2047]}
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JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.16 Active Video Threshold Active Video Threshold Low (1E)
7 AVT7 6 AVT6 5 AVT5 4 AVT4 3 AVT3 2 AVT2 1 AVT1 0 AVT0
Active Video Threshold High (1F)
7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Register 1F, 1E
Bit# 7-0
Bit Name AVT7-0
Description Active Threshold bits [7:0] The minimum value that should be considered not blank on the RGB input lines. This is used by the FS400 to compare to the input RGB when checking for active video to determine the SHV, EHV, SVV, and EVV values.
Range: {0:[255]}
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JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.17 OHO - Output Horizontal Offset Output Horizontal Offset Low (20)
7 OHO7 6 OHO6 5 OHO5 4 OHO4 3 OHO3 2 OHO2 1 OHO1 0 OHO0
Output Horizontal Offset High (21)
7 0 6 0 5 0 4 0 3 0 2 OHO10 1 OHO9 0 OHO8
Register 21, 20
Bit# 10-0
Bit Name OHO10-0
Description Output horizontal offset [10:0]. Horizontal displacement of the outgoing active video area image in pixels from the leading edge of outgoing horizontal sync.
Range:
NTSC: {126,[ 454]} PAL: {177, [ 566]}
Restrictions: 1. IHAW < IHS-1 2. NTSC:
HSC IHAW * 1 + + OHO < 894 64
3. Zoom NTSC:
HSC 2 * IHAW * 1 + + OHO < 894 64
4. PAL
HSC 2 * IHAW * 1 + + OHO < 1125 64
5. Zoom PAL:
HSC 2 * IHAW * 1 + + OHO < 1125 64
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JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.18 OVO - Output Vertical Offset Output Vertical Offset Low (22)
7 OVO7 6 OVO6 5 OVO5 4 OVO4 3 OVO3 2 OVO2 1 OVO1 0 OVO0
Output Vertical Offset High (23)
7 0 6 0 5 0 4 0 3 0 2 0 1 OVO9 0 OVO8
Register 23, 22
Bit# 9-0
Bit Name OVO9-0
Description Output vertical offset [9:0]. Vertical displacement of the outgoing active video area in lines from the beginning of the equalization pulses: line 1/263 for NTSC; line 311/623 for PAL.
Range: Restrictions: 1. At all times:
NTSC: {20,[ 262]} PAL: {25,[ 312]}
IVC - 1 1 ILS < * 2 1 - VSC 64
2. NTSC : ILS + OVO < 259 3. PAL: ILS + OVO < 310
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JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.19 HSC - Horizontal Scaling Coefficient Horizontal Scaling Coefficient (24)
7 HSC7 6 HSC6 5 HSC5 4 HSC4 3 HSC3 2 HSC2 1 HSC1 0 HSC0
Horizontal Scaling Coefficient (25)
7 6 5 4 3 2 1 0 HSC8
Register 25, 24
Bit# 8-0
Bit Name HSC8-0
Description Horizontal scaling coefficient, n [5:0]. Horizontal scaling factor = (1 + n/ 128)
Range: {0:[383]} Restrictions: 1. IHAW < IHS-1 2. NTSC:
HSC HAW * 1 + + OHO < 894 64
3. Zoom NTSC:
HSC 2 * HAW * 1 + + OHO < 894 64
4. PAL:
HSC HAW * 1 + + OHO < 1125 64
5. Zoom PAL:
HSC 2 * HAW * 1 + + OHO < 1125 64
Example: HSC = 3F hex; n = 63; Scaling factor = (1 + 63/128) = 1.49.
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JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.20 Contrast Coefficient Contrast Coefficient Low (26)
7 0 6 0 5 CON5 4 CON4 3 CON3 2 CON2 1 CON1 0 CON0
Contrast Coefficient High (27)
7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Register 26
Bit# 5-0
Bit Name CON5-0
Description Contrast Coefficient bits [5:0] The Contrast Coefficient provides a luma gain adjustment in the Luma Encoder. Contrast has an implicit denominator of 32.
Range: {0:[63]} Example: CON = 21 hex; 33 decimal; has a luma gain of 33/32 = 1.03 for a 3% increase in contrast. CON = 1f hex; 31 decimal; has a gain of 31/32 = .97; for a 3% decrease in contrast
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JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.21 Brightness Coefficient Brightness Coefficient Low (28)
7 BRT7 6 BRT6 5 BRT5 4 BRT4 3 BRT3 2 BRT2 1 BRT1 0 BRT0
Brightness Coefficient High (29)
7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Register 29, 28
Bit# 7-0
Bit Name BRT7-0
Description Brightness Coefficient bits [7:0] The Brightness Coefficient provides an offset adjustment in the Luma Encoder. BRT is a signed 8-bit number.
Range: {-128:[127]} Example: BRT = FF hex; -1 decimal; for a slight decrease in the average picture level.
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PRODUCT SPECIFICATION REV. NO. 1.7
4.5.22 Sharpness Coefficient Sharpness Coefficient Low (2A)
7 0 6 0 5 0 4 SHP4 3 SHP3 2 SHP2 1 SHP1 0 SHP0
Sharpness Coefficient High (2B)
7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Register 2B, 2A
Bit# 4-0
Bit Name SHP4-0
Description Sharpness Coefficient bits [4:0] The Sharpness Coefficient combines with the Flicker Filter Coefficient to provide a wide range of edge enhancement and detail vs. flicker. The Sharpness Coefficient controls the intensity of the edge enhancement (peaking function). Sharpness has an implicit denominator of 16.
Range: {0:[31]} Example: SHP = 10 hex; 16 decimal; for a sharpness of 100% (flat diagonal frequency response)
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JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
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PRODUCT SPECIFICATION REV. NO. 1.7
4.5.23 Flicker Filter Coefficient Flicker Filter Coefficient Low (2C)
7 0 6 0 5 0 4 FLK4 3 FLK3 2 FLK2 1 FLK1 0 FLK0
Flicker Filter Coefficient High (2D)
7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Register 2D, 2C
Bit# 4-0
Bit Name FLK4-0
Description Flicker Filter Coefficient bits [4:0] The Flicker Filter Coefficient combines with the Sharpness Coefficient to provide a wide range of edge enhancement and detail vs. flicker. The Flicker Filter Coefficient controls the width and height of the edge enhancement (impulse function). Flicker Filter has an implicit denominator of 16.
Range: {0:[21]} Filter Coefficients: FLK/64, 1-FLK/32, FLK/64 Example: FLK = 10 hex; 16 decimal; for a 1/4, 1/2, 1/4, three line average flicker filter. FLK = 0 hex; 0 decimal; for 0, 1, 0, no flicker filter. Note: If FLK is set to a value greater than 21, then the weight factor applied to the lines above and below the current line are greater than the current line creating a double line effect. Therefore, values > 21 are not recommended as they will create visual artifacts, but the FS400 does not prohibit these settings.
50
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
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PRODUCT SPECIFICATION REV. NO. 1.7
4.5.24 Color Saturation Coefficient Color Saturation Coefficient Low (2E)
7 0 6 0 5 CSC5 4 CSC4 3 CSC3 2 CSC2 1 CSC1 0 CSC0
Color Saturation Coefficient High (2F)
7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Register 2F, 2E
Bit# 5-0
Bit Name CSC5-0
Description Color Saturation Coefficient bits [5:0] The Color Saturation Coefficient provides a gain adjustment in the Chroma Encoder. Saturation has an implicit denominator of 32.
Range: {0:[63]} Example: CSC = 21 hex; 33 decimal; has a luma gain of 33/32 = 1.03; for a 3% increase in saturation. CSC = 1f hex; 31 decimal; has a gain of 31/32 = .97; for a 3% decrease in saturation
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JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.25 General Purpose Outputs General Purpose Outputs Low (34)
7 GPO7 6 GPO6 5 GPO5 4 GPO4 3 GPO3 2 GPO2 1 GPO1 0 GPO0
General Purpose Outputs High (35)
7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
Register 34
Bit# 7-0
Bit Name GPO7-0
Description General Purpose Output bits [7:0]. The General Purpose Output bits control the GPO pins on the FS400. The FS403 has all 8 GPO outputs available while the FS401 has only GPO6 and GPO0 available. On readback, the value read is the value written, not necessarily the voltage level. Reserved: Always set these bits to 0. Any other value will place the FS400 into a manufacturing test mode.
35
7-0
07-0
Note: When the internal microprocessor is running, GPO0 is under the control of the microprocessor (see CCR_FLT_FREQ in section 4.5.40). In order to modify the GPO register, one must first change the Configuration Command Register CCR_GPO at CCR address 0x20. After the CCR_GPO register is programmed, the exact same GPO value must be programmed into the General Purpose Outputs register (see above). Bit 0 of the GPO register is always reserved. When programming the CCR_GPO register it is ok to write an 8-bit value. The system will ignore bit 0. When programming the General Purpose Outputs register (see above), first read the register to get the current state of bit 0, change bits 1-7 as desired, then write the new value into the register.
52
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.26 SCR - Software Control Register Software Control Register Low (60)
7
ENICTBL
6
RSTCALC
5
RSTICAL
4
RSTVMODE
3
CLRMCC
2
OCAL
1
ENABLE
0
RESET
Software Control Register High (61)
7
SFLK3
6
SFLK2
5
SFLK1
4
SFLK0
3
MICALNEW
2
CNTRSML
1
DSVMDET
0
DSICAL
Reg 60 60
Bit# 0 1
Bit Name RESET ENABLE
60 60 60
2 3 4
OCAL CLRMCC RSTVMODE
60
5
RSTICAL
60
6
RSTCALC
60 61
7 0
ENICTBL DSICAL
61
1
DSVMDET
Description 0: Normal operation 1: Force software reset The internal micro-controller clears this bit. 0: Disable internal micro-controller 1: Enable internal micro-controller The internal micro-controller will not access any FS400 SIO registers while it is disabled. 0: Normal operation. 1: Turns on the output calibration image (color bars). 0: Leave Mode Change Complete (MCC) status bit unchanged 1: Clear MCC (the internal micro-controller clears this bit). 0: Normal operation 1: Reset video mode. Forces the internal micro-controller to redetermine the size and speed of the current video mode and to reacquire the input calibration. The internal micro-controller clears this bit. 0: Normal operation 1: Resets the input calibration. This forces the internal micro-controller to re-acquire the input calibration. If input calibration table is enabled (ENICTBL = 1), then the table entry for this video mode is also reset. The internal micro-controller clears this bit. 0: Normal operation 1: Forces the internal micro-controller to re-calculate the low level FS400 registers for the current mode. This does not affect the video mode or input calibration. The internal micro-controller clears this bit. 0: Input calibration is not stored in the input calibration table. 1: Input calibration is stored in the input calibration table. 0: Normal operation 1: Disables the input calibration processing. DSICAL is used to bypass the internal micro-controller's input calibration sampling algorithm. NOTE: This bit is used only when an external processor wants to bypass the internal micro-controller's input calibration algorithm. It should be set to 0 for most applications. 0: Normal operation 1: Disable video mode detect. The internal micro-controller will not sample IHC and IVC to detect a video mode change. NOTE: This bit is used only when an external processor wants to bypass the internal micro-controller's video mode detect algorithm. It 53
COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
JANUARY 24, 2007
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
61 61 61
2 3 7-4
CNTRSML MICALNEW SFLK3-0
should be set to 0 for most applications. 0: Small input images are scaled horizontally to fill the output device. 1: Small input images are centered on the output device. 0: Normal operation 1: There is new manual input calibration information. The internal micro-controller clears this bit. Adjusts the flicker filter from 0 (no flicker filter) to 8 (maximum flicker filter). SFLK is different from the hardware register FLK. SFLK is normalized for compression.
Reset Value:
0x8402
54
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.27 SSR - Software Status Register Software Status Register Low (62)
7
0
6
HSYNCACT
5
VSYNCACT
4
ICALAQRD
3
MCC
2
MCS
1
ERROR
0
READY
Software Status Register High (63)
7
CHKSUM7
6
CHKSUM6
5
CHKSUM5
4
CHKSUM4
3
CHKSUM3
2
CHKSUM2
1
CHKSUM1
0
CHKSUM0
Reg 62 62
Bit# 0 1
Bit Name READY ERROR
62
2
MCS
62
3
MCC
62
4
ICALAQRD
62 62 63
5 6 7-0
VSYNCSACT HSYNCACT CHKSUM7-0
Description 0: Internal controller is initializing after reset 1: Internal controller is ready 0: The video mode parameters are all within range 1: A video mode parameter is out of range and the mode cannot be calculated. The following conditions cause an error: IHC < 32 IVC < 32 HAT < 20% VAT < 20% TVP < 128 TVL < 128 Mode Change Start 0: Video mode change is not in progress. 1: Video mode change is in progress. The internal micro-controller sets this bit to 1 after it detects a change in the size or speed of the input video mode. The controller clears this bit after it has completed the calculations for the new mode. Mode Change Complete 0: Video mode change is not complete 1: Video mode change is complete NOTE: This bit is set when a mode change is complete and cleared by writing a 1 to the CLRMCC bit in the SCR Input Calibration Acquired 0: The internal micro-controller has not yet read an acceptable set of values from the SHV, EHV, SVV, and EVV registers and is using the default values for HAT, SHV, VAT, and SVV. 1: The internal micro-controller has read acceptable input calibration values and is using them. 0: No VSync activity during last 100ms interval. 1: VSync activity during last 100ms interval was detected. 0: No HSync activity during last 100ms interval. 1: HSync activity during last 100ms interval was detected. Internal micro-controller ROM and RAM checksum. NOTE: The checksum for version 30 is 0xAF.
NOTE: It is possible to write to this register, however doing so will produce unpredictable results.
55
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.28 HCRS - Hardware Control Register Shadow Hardware Control Register Shadow Low (64)
7
PEDSTL
6
CBP
5
LNTCH
4
YCOFF
3
COMPOFF
2
ADCOFF
1
CLKOFF
0
0
Hardware Control Register Shadow High (65)
7
0
6
0
5
OFMT1
4
OFMT0
3
PAL_NTSC
2
PROG_INT
1
TV_CLK1
0
TV_CLK0
Reg 64 64 64 64 64 64 64 65
Bit# 1 2 3 4 5 6 7 1-0
Bit Name CLKOFF ADCOFF COMPOFF YCOFF LNTCH CBP PEDSTL TV_CLK1-0
65 65 65
2 3 5-4
PROG_INT PAL_NTSC OFMT1-0
Description 0: FS400 clocks powered on. 1: FS400 clocks powered off. 0: A/D converter powered on. 1: A/D converter powered off. 0: Composite D/A converter powered on. 1: Composite D/A converter powered off. 0: Y/C & Chroma D/A converter powered on. 1: Y/C & Chroma D/A converter powered off. 0: Bypass luminance notch filter. 1: Insert luminance notch filter. 0: Bypass chroma bandpass filter. 1: Insert chroma bandpass filter. 0: Bypass pedestal 1: Insert US NTSC black pedestal TV Clock Select 00 = 4FSC crystal or oscillator 01 = non-subcarrier crystal or oscillator 10 = 8FSC crystal or oscillator 0 = Interlaced Output 1 = Progressive Output 0 = NTSC 1 = PAL Output Format 00 = Y/C and Composite Video 01 = RGB 10 = YUV 11 = YUV
Reset Value:
0x0080
Typical Output Mode Settings: TV Mode NTSC PAL VGA SVGA 100Hz PAL Progressive NTSC (720x480) Super NTSC (1280x480) Super PAL (1280x575)
TV_CLK 0 0 2 2 1 1 2 2
PROG_INT 0 0 1 1 0 1 0 0
PAL_NTSC 0 1 0 1 1 0 0 1
NOTE: Any change to TV_CLK, PROG_INT, or PAL_NTSC causes the internal micro-controller to initialize the HOHOS, HOVOS, TVL, TVP, and CCR_FREQUENCY registers to defaults appropriate to the new output mode.
56
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.29 HCRES - Hardware Control Register Extended Shadow Hardware Control Register Extended Shadow Low (66)
7
0
6
0
5
VGAINTDET
4
0
3
0
2
FREEZE
1
RGBGAIN
0
ZOOM
Hardware Control Register Extended Shadow High (67)
7
0
6
0
5
0
4
0
3
0
2
BIPGEN2
1
BIPGEN1
0
BIPGEN0
Reg 66 66 66 66 67
Bit# 0 1 2 5 2-0
Bit Name ZOOM RGBGAIN FREEZE VGAINTDET BIPGEN
Description 0: Normal operation 1: Zoom mode 0: 1x input gain 1: 1.43x input gain 0: Continuous update 1: Freeze frame 0: Ignore interlaced input. 1: Detect interlaced input. Built-in Pattern Generator: 000 = Invalid 001 = All Waveforms 010 = 100% Color Bars 011 = 75% Color Bars 100 = Cross Hatch 101 = Red Gradient 110 = Green Gradient 111 = Blue Gradient NOTE: Only has effect when OCAL bit in SCR register is set.
Reset Value:
0x0320
57
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.30 HPO - Horizontal Position Offset Horizontal Position Offset Low (68)
7
HPO7
6
HPO6
5
HPO5
4
HPO4
3
HPO3
2
HPO2
1
HPO1
0
HPO0
Horizontal Position Offset High (69)
7
HPO15
6
HPO14
5
HPO13
4
HPO12
3
HPO11
2
HPO10
1
HPO9
0
HPO8
Description: This offsets the horizontal position of the input capture window. A positive number moves the capture widow to the right and a negative number moves the input capture window to the left. HPO only has meaning if the ZOOM bit in HCRES is 0. If the value written to HPO is beyond the internally calculated limit, the maximum (or minimum in case of a negative number) will be written back to the HPO register. An external processor can then read HPO to determine if the last value written to HPO was beyond the limit. NOTE: It can take up to 25ms for the internal micro-controller calculates the limits for HPO, VPO, HSS, VSS, HPP, and VPP. These registers should not be read until 10ms after writing to any of these registers. Range: {-32768 : +32767} 2's Complement Reset Value: 0x0000
58
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.31 VPO - Vertical Position Offset Vertical Position Offset Low (6A)
7
VPO7
6
VPO6
5
VPO5
4
VPO4
3
VPO3
2
VPO2
1
VPO1
0
VPO0
Vertical Position Offset High (6B)
7
VPO15
6
VPO14
5
VPO13
4
VPO12
3
VPO11
2
VPO10
1
VPO9
0
VPO8
Description: This offsets the vertical position of the input capture window. A positive number moves the capture widow down and a negative number moves the input capture window up. VPO only has meaning if the ZOOM bit in HCRES is 0. If the value written to VPO is beyond the internally calculated limit, the maximum (or minimum in case of a negative number) will be written back to the VPO register. An external processor can then read VPO to determine if the last value written to VPO was beyond the limit. NOTE: It can take up to 25ms for the internal micro-controller calculates the limits for HPO, VPO, HSS, VSS, HPP, and VPP. These registers should not be read until 10ms after writing to any of these registers. Range: {-32768 : +32767} 2's Complement Reset Value: 0x0000
59
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.32 HSS - Horizontal Scale Step Horizontal Scale Step Low (6C)
7
HSS7
6
HSS 6
5
HSS 5
4
HSS 4
3
HSS 3
2
HSS 2
1
HSS 1
0
HSS 0
Horizontal Scale Step High (6D)
7
HSS 15
6
HSS 14
5
HSS 13
4
HSS 12
3
HSS 11
2
HSS 10
1
HSS 9
0
HSS 8
Description: This offsets the horizontal scale from its nominal value. A positive number stretches the image and a negative number compresses the image. If the value written to HSS is beyond the internally calculated limit, the maximum (or minimum in case of a negative number) will be written back to the HSS register. An external processor can then read HSS to determine if the last value written to HSS was beyond the limit. NOTE: It can take up to 25ms for the internal micro-controller calculates the limits for HPO, VPO, HSS, VSS, HPP, and VPP. These registers should not be read until 10ms after writing to any of these registers. Range: {-32768 : +32767} 2's Complement Reset Value: 0x0000
60
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.33 VSS - Vertical Scale Step Vertical Scale Step Low (6E)
7
VSS7
6
VSS 6
5
VSS 5
4
VSS 4
3
VSS 3
2
VSS 2
1
VSS 1
0
VSS 0
Vertical Scale Step High (6F)
7
VSS 15
6
VSS 14
5
VSS 13
4
VSS 12
3
VSS 11
2
VSS 10
1
VSS 9
0
VSS 8
Description: This offsets the vertical scale from its nominal value. A positive number stretches the image and a negative number compresses the image. If the value written to VSS is beyond the internally calculated limit, the maximum (or minimum in case of a negative number) will be written back to the VSS register. An external processor can then read VSS to determine if the last value written to VSS was beyond the limit. NOTE: It can take up to 25ms for the internal micro-controller calculates the limits for HPO, VPO, HSS, VSS, HPP, and VPP. These registers should not be read until 10ms after writing to any of these registers. Range: {-32768 : +32767} 2's Complement Reset Value: 0x0000
61
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.34 HPP - Horizontal Pan Position Horizontal Pan Position Low (70)
7
HPP7
6
HPP6
5
HPP5
4
HPP4
3
HPP3
2
HPP2
1
HPP1
0
HPP0
Horizontal Pan Position High (71)
7
HPP15
6
HPP14
5
HPP13
4
HPP12
3
HPP11
2
HPP10
1
HPP9
0
HPP8
Description: This controls the horizontal pan window position. A value of 0 will set the pan window to the left edge of the input image. As HPP increases, the pan window will move to the right. HPP only has meaning if the ZOOM bit in HCRES is 1. If the value written to HPP is beyond the internally calculated limit, the maximum (or minimum in case of a negative number) will be written back to the HPP register. An external processor can then read HPP to determine if the last value written to HPP was beyond the limit. NOTE: It can take up to 25ms for the internal micro-controller calculates the limits for HPO, VPO, HSS, VSS, HPP, and VPP. These registers should not be read until 10ms after writing to any of these registers. Range: {-32768 : +32767} 2's Complement Reset Value: 0x0000
62
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.35 VPP - Vertical Pan Position Vertical Pan Position Low (72)
7
VPP7
6
VPP6
5
VPP5
4
VPP4
3
VPP3
2
VPP2
1
VPP1
0
VPP0
Vertical Pan Position High (73)
7
VPP15
6
VPP14
5
VPP13
4
VPP12
3
VPP11
2
VPP10
1
VPP9
0
VPP8
Description: This controls the vertical pan window position. A value of 0 will set the pan window to the top edge of the input image. As VPP increases, the pan window will move down. VPP only has meaning if the ZOOM bit in HCRES is 1. If the value written to VPP is beyond the internally calculated limit, the maximum (or minimum in case of a negative number) will be written back to the VPP register. An external processor can then read VPP to determine if the last value written to VPP was beyond the limit. NOTE: It can take up to 25ms for the internal micro-controller calculates the limits for HPO, VPO, HSS, VSS, HPP, and VPP. These registers should not be read until 10ms after writing to any of these registers. Range: {-32768 : +32767} 2's Complement Reset Value: 0x0000
63
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.36 TVP - TV Pixels TV Pixels Low (74)
7
TVP7
6
TVP6
5
TVP5
4
TVP4
3
TVP3
2
TVP2
1
TVP1
0
TVP0
TV Pixels High (75)
7
TVP15
6
TVP14
5
TVP13
4
TVP12
3
TVP11
2
TVP10
1
TVP9
0
TVP8
Description: Tells the internal controller the total number of usable pixels on the output device in a horizontal line. If the value written to TVP is beyond the limit, the new mode will not be calculated and the ERROR bit in SSR will be set. Any change to TV_CLK, PROG_INT, or PAL_NTSC fields in the HCRS register causes the internal micro-controller to initialize TVP register to a default value appropriate to the new output mode.
TV Mode NTSC PAL VGA SVGA 100Hz PAL Progressive NTSC (720x480) Super NTSC (1280x480) Super PAL (1280x575) TVP 658 820 640 800 908 658 914 914
Range: {+128 : +2047} Reset Value: 0x0292 (658.)
64
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.37 TVL - TV Lines TV Lines Low (76)
7
TVL7
6
TVL6
5
TVL5
4
TVL4
3
TVL3
2
TVL2
1
TVL1
0
TVL0
TV Lines High (77)
7
TVL15
6
TVL14
5
TVL13
4
TVL12
3
TVL11
2
TVL10
1
TVL9
0
TVL8
Description: Tells the internal controller the total number of usable lines on the output device. If the value written to TVL is beyond the limit, the new mode will not be calculated and the ERROR bit in SSR will be set. Any change to TV_CLK, PROG_INT, or PAL_NTSC fields in the HCRS register causes the internal micro-controller to initialize TVL register to a default value appropriate to the new output mode.
TV Mode NTSC PAL VGA SVGA 100Hz PAL Progressive NTSC (720x480) Super NTSC (1280x480) Super PAL (1280x575) TVL 412 496 480 600 540 412 412 496
Range: {+128 : +2047} Reset Value: 0x019C (412.)
65
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.38 CCR - Configuration Command Register Configuration Command Register Low (78)
7
ADDR7
6
ADDR 6
5
ADDR 5
4
ADDR 4
3
ADDR 3
2
ADDR 2
1
ADDR 1
0
ADDR 0
Configuration Command Register High (79)
7
0
6
0
5
0
4
0
3
CMD3
2
CMD2
1
CMD1
0
CMD0
Reg 78 79
Bit# 7-0 3-0
Bit Name ADDR 7-0 CMD3-0
Description Parameter Address This field contains the address of the configuration parameter to be accessed. Command 0000 0001 0010 Command complete. The internal controller writes this. Read from the configuration parameter. After the command is complete CDR contains the data. Write to the configuration parameter. The CDR must contain the data to write before CCR is written.
The CCR and CDR registers are used to access constants and variables inside the internal microcontroller. The definitions of these parameters are found in section 4.5.40. To read from a configuration parameter, write 0001 to the command field and the configuration parameter address in the address field of the CCR. These values must be written with one operation. Next, poll the CCR until it becomes zero. Be sure to include a delay between polling reads to prevent stopping the internal CPU from having access to the SIO registers. Then read the CDR to retrieve the value of the specified configuration parameter. To write to a configuration parameter, write the data to the CDR. Next, write 0010 to the command field and the configuration parameter address in the address field of the CCR. When the CCR because zero, the write operation is complete. Be sure to include a delay between polling reads to prevent stopping the internal CPU from having access to the SIO registers.
Reset Value: 0x0000
66
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.39 CDR - Configuration Data Register Configuration Data Register Low (7A)
7
CDR
6
CDR 6
5
CDR 5
4
CDR 4
3
CDR 3
2
CDR 2
1
CDR 1
0
CDR 0
Configuration Data Register High (7B)
7
CDR
6
CDR 14
5
CDR 13
4
CDR 12
3
CDR 11
2
CDR 10
1
CDR 9
0
CDR 8
Description: Contains the value of the configuration parameter after a CDR read command is complete. Contains the new value of a configuration parameter before a CDR write is executed. Reset Value: 0x0000
67
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.40 HOHOS - Hardware Output Horizontal Offset Shadow Hardware Output Horizontal Offset Shadow Low (7C)
7
HOHOS 7
6
HOHOS 6
5
HOHOS 5
4
HOHOS 4
3
HOHOS 3
2
HOHOS 2
1
HOHOS 1
0
HOHOS 0
Hardware Output Horizontal Offset Shadow High (7D)
7
HOHOS 15
6
HOHOS 14
5
HOHOS 13
4
HOHOS 12
3
HOHOS 11
2
HOHOS 10
1
HOHOS 9
0
HOHOS 8
Description: Horizontal displacement of the outgoing active video area image in pixels from the leading edge of outgoing horizontal sync. Any change to TV_CLK, PROG_INT, or PAL_NTSC fields in the HCRS register causes the internal micro-controller to initialize HOHOS register to a default value appropriate to the new output mode.
TV Mode NTSC PAL VGA SVGA 100Hz PAL Progressive NTSC (720x480) Super NTSC (1280x480) Super PAL (1280x575) HOHOS 178 230 132 176 180 178 290 290
Reset Value:
0x00B2 (178.)
68
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.5.41 HOVOS - Hardware Output Vertical Offset Shadow Hardware Output Vertical Offset Shadow Low (7E)
7
HOVOS 7
6
HOVOS 6
5
HOVOS 5
4
HOVOS 4
3
HOVOS 3
2
HOVOS 2
1
HOVOS 1
0
HOVOS 0
Hardware Output Vertical Offset Shadow High (7F)
7
HOVOS 15
6
HOVOS 14
5
HOVOS 13
4
HOVOS 12
3
HOVOS 11
2
HOVOS 10
1
HOVOS 9
0
HOVOS 8
Description: Vertical displacement of the outgoing active video area in lines from the beginning of the equalization pulses: line 1/263 for NTSC; line 311/623 for PAL. Any change to TV_CLK, PROG_INT, or PAL_NTSC fields in the HCRS register causes the internal micro-controller to initialize HOVOS register to a default value appropriate to the new output mode.
TV Mode NTSC PAL VGA SVGA 100Hz PAL Progressive NTSC (720x480) Super NTSC (1280x480) Super PAL (1280x575) HOVOS 38 44 40 36 38 38 38 44
Reset Value:
0x0026 (38.)
69
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
4.6 Configuration Values
Name CCR_VERSION CCR_FREQUENCY Addr 0x00 0x01 R/W R R/W Size 8 8 Reset Value 30 112 Description The internal micro-controller's version number. (First silicon = 30, 4/99) The speed of the FS400 expressed as: (Clock Speed / 14.31mHz) * 32 The reset value assumes the FS400 clock speed is 50mHz. The analog filter frequency threshold. This value is expressed as : (Threshold Clock Speed / 14.31mHz) * 32 The reset value assumes a 28mHz threshold. When the IHS register exceeds this frequency, GPO0 is set to a 1. The value the internal micro-controller writes into the FS400 AVT register when RGBGAIN is off. The value the internal micro-controller writes into the FS400 AVT register when RGBGAIN is on. Minimum HAT (Horizontal Active) value allowed. Values of HAT lower than this will cause the input calibration algorithm to use the default HAT value (DEF_HAT). Expressed as a percentage of the horizontal total * 65536. Maximum HAT (Horizontal Active) value allowed. Values of HAT higher than this will cause the input calibration algorithm to use the default HAT value (DEF_HAT). Expressed as a percentage of the horizontal total * 65536. The default HAT (Horizontal Active) value is used when the internal micro-controller has not been able to acquire a valid set of horizontal input calibration values. Expressed as a percentage of the horizontal total * 65536. Minimum SHV (Start Horizontal Video) value allowed. Values of SHV lower than this will cause the input calibration algorithm to use the default SHV value (DEF_SHV). Expressed as a percentage of the horizontal total * 65536. Maximum SHV (Start Horizontal Video) value allowed. Values of SHV higher than this will cause the input calibration algorithm to use the default SHV value (DEF_SHV). Expressed as a percentage of the horizontal total * 65536. The default SHV (Start Horizontal Video) value is used when the internal microcontroller has not been able to acquire a valid set of horizontal input calibration
COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
CCR_FLT_FREQ
0x02
R/W
8
63
CCR_AVT CCR_AVT_RGBGAIN CCR_MIN_HAT
0x03 0x04 0x05
R/W R/W R/W
8 8 16
64 128 32768
CCR_MAX_HAT
0x06
R/W
16
64881
CCR_DEF_HAT
0x07
R/W
16
55706
CCR_MIN_SHV
0x08
R/W
16
1311
CCR_MAX_SHV
0x09
R/W
16
32767
CCR_DEF_SHV
0x0A
R/W
16
9830
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CCR_MIN_VAT
0x0B
R/W
16
32768
CCR_MAX_VAT
0x0C
R/W
16
64881
CCR_DEF_VAT
0x0D
R/W
16
63898
CCR_MIN_SVV
0x0E
R/W
16
1311
CCR_MAX_SVV
0x0F
R/W
16
32767
CCR_DEF_SVV
0x10
R/W
16
1638
CCR_COUNTER
0x11
R/W
8
0
CCR_PIXEL_SIZE
0x12
R/W
16
CCR_LINE_SIZE
0x13
R/W
16
0
CCR_MICAL_HAT
0x14
R/W
16
55706
CCR_MICAL_VAT
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0x15
R/W
16
63898 71
values. Expressed as a percentage of the horizontal total * 65536. Minimum VAT (Vertical Active) value allowed. Values of VAT lower than this will cause the input calibration algorithm to use the default VAT value (DEF_VAT). Expressed as a percentage vertical total * 65536. Maximum VAT (Vertical Active) value allowed. Values of HAT higher than this will cause the input calibration algorithm to use the default HAT value (DEF_HAT). Expressed as a percentage vertical total * 65536. The default VAT (Vertical Active) value is used when the internal micro-controller has not been able to acquire a valid set of vertical input calibration values. Expressed as a percentage vertical total * 65536. Minimum SVV (Start Vertical Video) value allowed. Values of SVV lower than this will cause the input calibration algorithm to use the default SVV value (DEF_SVV). Expressed as a percentage vertical total * 65536. Maximum SVV (Start Vertical Video) value allowed. Values of SVV higher than this will cause the input calibration algorithm to use the default SVV value (DEF_SVV). Expressed as a percentage vertical total * 65536. The default SVV (Start Vertical Video) value is used when the internal microcontroller has not been able to acquire a valid set of vertical input calibration values. Expressed as a percentage vertical total * 65536. Reads the internal micro-controller's counter. The counter runs at a frequency of OSC1 / 786432. If OSC1 is 14.31mHz, the COUNTER frequency is 18.20Hz. The size of 1 horizontal pixel expressed as a percentage of the horizontal total * 65536. This value is useful in computing offset of the manual input calibration values. The size of 1 vertical line expressed as a percentage of the vertical total * 65536. This value is useful in computing offset of the manual input calibration values. The HAT (Horizontal Active) value is used when the internal micro-controller is in manual input calibration mode (DSICAL bit in SCR is set). Expressed as a percentage of the horizontal total * 65536. The VAT (Vertical Active) value is used
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CCR_MICAL_SHV
0x16
R/W
16
9830
CCR_MICAL_SVV
0x17
R/W
16
1638
CCR_HSS_MIN CCR_HSS_MAX CCR_VSS_MIN CCR_VSS_MAX CCR_HPX_MIN
0x18 0x19 0x1A 0x1B 0x1C
R/W R/W R/W R/W R/W
16 16 16 16 16
CCR_HPX_MAX
0x1D
R/W
16
CCR_VPX_MIN
0x1E
R/W
16
CCR_VPX_MAX
0x1F
R/W
16
CCR_GPO
0x20
R/W
16
0 or 1
CCR_IHC CCR_IVC CCR_HAT
0x21 0x22 0x23
R/W R/W R/W
16 16 16
when the internal micro-controller is in manual input calibration mode (DSICAL bit in SCR is set). Expressed as a percentage of the vertical total * 65536. The SHV (Start Horizontal Video) value is used when the internal micro-controller is in manual input calibration mode (DSICAL bit in SCR is set). Expressed as a percentage of the horizontal total * 65536. The SVV (Start Vertical Video) value is used when the internal micro-controller is in manual input calibration mode (DSICAL bit in SCR is set). Expressed as a percentage of the vertical total * 65536. Minimum value of HSS for the current video mode. Maximum value of HSS for the current video mode. Minimum value of VSS for the current video mode. Maximum value of VSS for the current video mode. In zoom mode (ZOOM bit in HCRES is set), contains the minimum value of HPP for the current video mode. When not in zoom mode, contains the minimum value of HPO for the current mode. In zoom mode (ZOOM bit in HCRES is set), contains the maximum value of HPP for the current video mode. When not in zoom mode, contains the maximum value of HPO for the current mode. In zoom mode (ZOOM bit in HCRES is set), contains the minimum value of VPP for the current video mode. When not in zoom mode, contains the minimum value of VPO for the current mode. In zoom mode (ZOOM bit in HCRES is set), contains the maximum value of VPP for the current video mode. When not in zoom mode, contains the maximum value of VPO for the current mode. The value written to the FS400 GPO register. The internal micro-controller controls the state of bit 0. All other bits are available for general-purpose output. The internal micro-controller's version of the FS400 IHC register. The internal micro-controller's version of the FS400 IVC register. The current HAT value. This can either be the default HAT (DEF_HAT) or a HAT calculated from the SHV and EHV registers. Expressed as a percentage of the
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CCR_SHV
0x24
R/W
16
CCR_VAT
0x25
R/W
16
CCR_SVV
0x26
R/W
16
CCR_ICAL_TABLE_0_IVC CCR_ICAL_TABLE_0_IHC CCR_ICAL_TABLE_0_HAT CCR_ICAL_TABLE_0_SHV CCR_ICAL_TABLE_0_VAT CCR_ICAL_TABLE_0_SVV CCR_ICAL_TABLE_1_IVC CCR_ICAL_TABLE_1_IHC CCR_ICAL_TABLE_1_HAT CCR_ICAL_TABLE_1_SHV CCR_ICAL_TABLE_1_VAT CCR_ICAL_TABLE_1_SVV CCR_ICAL_TABLE_2_IVC CCR_ICAL_TABLE_2_IHC CCR_ICAL_TABLE_2_HAT CCR_ICAL_TABLE_2_SHV CCR_ICAL_TABLE_2_VAT CCR_ICAL_TABLE_2_SVV CCR_ICAL_TABLE_3_IVC CCR_ICAL_TABLE_3_IHC
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0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 73
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
horizontal total * 65536. The current SHV value. This can either be the default SHV (DEF_SHV) or a SHV calculated from the SHV and EHV registers. Expressed as a percentage of the horizontal total * 65536. The current VAT value. This can either be the default VAT (DEF_VAT) or a VAT calculated from the SVV and EVV registers. Expressed as a percentage of the vertical total * 65536. The current SVV value. This can either be the default SVV (DEF_SVV) or a SVV calculated from the SVV and EVV registers. Expressed as a percentage of the vertical total * 65536. The IVC value that this table entry represents. The IHC value that this table entry represents. The accumulated HAT value used for this video mode. The accumulated SHV value used for this video mode. The accumulated VAT value used for this video mode. The accumulated SVV value used for this video mode. The IVC value that this table entry represents. The IHC value that this table entry represents. The accumulated HAT value used for this video mode. The accumulated SHV value used for this video mode. The accumulated VAT value used for this video mode. The accumulated SVV value used for this video mode. The IVC value that this table entry represents. The IHC value that this table entry represents. The accumulated HAT value used for this video mode. The accumulated SHV value used for this video mode. The accumulated VAT value used for this video mode. The accumulated SVV value used for this video mode. The IVC value that this table entry represents. The IHC value that this table entry
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CCR_ICAL_TABLE_3_HAT CCR_ICAL_TABLE_3_SHV CCR_ICAL_TABLE_3_VAT CCR_ICAL_TABLE_3_SVV
0x3B 0x3C 0x3D 0x3E
R/W R/W R/W R/W
16 16 16 16
0 0 0 0
represents. The accumulated HAT value used for this video mode. The accumulated SHV value used for this video mode. The accumulated VAT value used for this video mode. The accumulated SVV value used for this video mode.
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5. Functional Description
ADC_SEL R_DIG G_DIG B_DIG Multiplexer Built In Pattern VSYNC HSYNC CSYNC FLP_RST Video Encoder YUV/RGB Matrix Multiplexer 9 Bit DAC 9 Bit DAC 9 Bit DAC LUMA_R_V CVBS_G_Y CHROMA_B_U
Gain
RED GRN BLU
8 Bit ADC 8 Bit ADC 8 Bit ADC
RGB/YUV Matrix
OSD Overlay
Vertical Scaler VGA PLL
Horizontal Scaler /3
Clamp
RGB_OSD
HALFTONE
VGA_HSYNC VGA_VSYNC Clock Generator
DRAM PLL
Xtal_N Xtal_P
Serial Bus Interface
Embedded Processor
Figure 5. Functional Block Diagram (RGB7-0 and A/D_SEL\ omitted on FS401)
Details of how to connect and setup the FS400 are included in this section. Overall design principles are in the Architectural Overview section. Operation of the FS400 is divided into four sections: * * * * * Capture Engine Frame Store Controller Encoder Engine Serial Control Port Embedded Microprocessor
5.1 Capture Engine
A/D Converters, Built In Pattern Generator, RGB/YUV Matrix, Vertical Scaler and Flicker Filter comprise the Capture Engine.
5.1.1 Timing and Control
Timing of the Capture Engine is derived from the Input Control Block which contains a series of counters and decoders synchronized to the A/D sample clock, ADCK. ADCK is derived from a phase locked loop referenced to the leading edge of horizontal sync. Sync polarity is auto-detected by sensing the leading edge of horizontal sync HS_IN and vertical sync, VS_IN. This edge is the reference for the phase-locked loop tracking the horizontal pixel count and the vertical line counter. Registers that interface with the Capture Timing and Control block are: 1. IHS
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4. SHV (read only) 75
NTSC_PAL
SIO_DATA
4 BUTTON
SIO_CLK
SIO_10/7
SIO_A0
EXT_CPU
COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
OSD_EN
External Sync DRAM Memory
Flicker Filter
VGA Cache
TV Cache
7. EVV (read only)
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2. IHC (read only) 3. IVC (read only)
5. EHV (read only) 6. SVV (read only)
8. AVT
Capture Control also coordinates hand off of data to the Frame Store Controller. Input Horizontal Samples, IHS is the 11-bit terminal count of the number of pixels per horizontal line between sync pulses. IHS is the value programmed into the ADCK phase-locked-loop. If, for example there are to be 800 samples per incoming line, then IHS must be programmed to be 799. Input Horizontal Count, IHC is the number of encoder clock pulses on the selected OSC clock that occur between horizontal sync pulses. This count is stored in the IHC register that can be read via the serial bus for automatic detection of the format of incoming video. Input Vertical Count, IVC is the 12-bit terminal count of the number of lines that occur between the vertical sync pulses. This count is stored in the IVC register that can be read via the serial bus for automatic detection of the format of incoming video. Start Horizontal Active VGA, SHV is the number of ADC clock pulses that occur from the start of the horizontal sync pulse to the detection of incoming active video. This is used to permit an accurate positioning of the incoming VGA on the TV. End Horizontal Active VGA, EHV is the number of ADC clock pulses that occur from the start of the horizontal sync pulse to the end of detected incoming active video. This is used to permit an accurate positioning of the incoming VGA on the TV. Start Vertical Active VGA, SVV is the number of lines that occur from the start of the vertical sync pulse to the detection of incoming active video. This is used to permit an accurate positioning of the incoming VGA on the TV. End Vertical Active VGA, EVV is the number of lines that occur from the start of the vertical sync pulse to the end of detected incoming active video. This is used to permit an accurate positioning of the incoming VGA on the TV.
5.1.2 Clamps
Incoming RGB video signals must be AC coupled to the A/D converters. Preceding each A/D converter is an FET clamp switch which establishes the black reference level of each video signal by shorting the A/D converter input to ground when the clamp signal is active. Clamp timing is derived internally from the HS_IN input. A digital output, CLAMP_REF = H, when the clamp is active. CLAMP_REF and VGACLKDIV polarity are set by the VGAREFPOL bit in the CRE register.
5.1.3 Analog-to-Digital Converters
Bottom reference voltage of the A/D converters is ground. Top reference voltage, VT is a high impedance input that is applied via voltage followers to the reference ladder network of each A/D converter. VT must be de-coupled with a 0.1F capacitor to ground. VT can be derived from the internal reference voltage, VREF by splitting the resistor connected to IREF as described in the 5.3.5 Digital-to-Analog Converters section. To avoid aliasing effects, incoming RGB video signals should be filtered by a low pass filter prior to the AC coupling capacitor. Filter cutout frequency should be set at half the highest expected sampling rate of the A/D converter clock, ADCK. A simple two element RC filter is adequate. 20MHz is typically used as a cut off frequency. Phase of ADCK is set by the Command Register Extended VGACLKPOL bit. By flipping the phase of the sampling clock by 180, the sampling points can be positioned closer to the center of incoming pixels. Figure 6 shows optimum sampling of VGA pixels on the rising edge of the ADCLK signal, when synchronous sampling is chosen.
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VGAPIX ADCLK
Figure 6. FAZE Sets ADCK Sampling Edge on Incoming Pixels
A/D converter power can be disconnected by setting the CR register ADCOFF bit.
5.1.4 24-bit Digital RGB Port (FS403 only)
Extra pins are included on the FS403 package to incorporate a 24-bit TTL compatible RGB input port. Either analog or digital inputs can be selected by the level on the EXADSEL pin. With the 24-bit RGB port enabled, incoming pixels may be derived directly from an external digital RGB source or from analog RGB via triple 8-bit A/D converters.
5.1.5 Built In Pattern Generator
BIPGEN in the CRE register selects one of several test patterns instead of the incoming video. If the "All Waveforms" option is set (001), the pattern looks as follows:
Figure 7: BiPGEN Image
The 512x512 chart is inserted into a 768x768 pixel frame, displaced 128 pixels from the left boundary and 128 pixels from the upper boundary. Color bars are each 64 pixels wide.
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5.1.6 Digital RGB Multiplexer
The EXADSEL pin in conjunction with BIPGEN in the CRE register controls a triple 24-bit multiplexer that selects the source of RGB data to be supplied to the digital gain block. 24-bit RGB data can be accepted from: * * * TTL compatible RGB input port A/D converter outputs BiPGen, the internal test pattern generator
5.1.7 RGB Gain
Following each A/D converter is a digital gain stage that allows the A/D converter to accommodate either 700 mV or 1000 mV RGB input video signals. Gain is set by the RGBGAIN bit of the Command Register. When using RGBGAIN, VADCREF should be set to 1000 mV.
5.1.8 RGB/YUV Matrix
Pixels are converted from the 24-bit RGB format to the 24-bit YUV format by an RGB/YUV matrix. UV data is filtered and decimated prior to realignment with Y data forming a 16-bit YUV422 data stream.
5.1.9 Vertical Scaler
16-bit YUV422 data from the Transcoder is passed to the Vertical Scaler that operates on columns of pixels. Programming the VSC registers sets vertical scale factor. VSC is the Vertical Scale Coefficient, n which determines the vertical scaling factor: Vertical Scaling = (1 - VSC/256) n is the reduction (caused by the scaling filter), modulo 256, in the number incoming vertical lines. With a range: 0 n 192; 1 VSC 1/4.
5.1.10 Flicker Filter
The FS400 flicker filter includes a variable vertical filter response in addition to a sharpness function. The vertical averaging part of the filter is decomposed into an impulse function (no filtering) and a vertical flicker function. Adjusting the FLK Coefficient modifies the vertical filter from no filtering (FLK = 0) to a Three Line Average (FLK = 21), giving the user a wide choice in filtering options. A value of 16 provides the normal 3 line flicker filter response of 1/4, 1/2, and 1/4. In addition to the variable vertical settings, the FS400 flicker filter has a sharpness function. This function is a two dimensional peaking function with accentuates the joint high vertical - high horizontal spatial frequencies. The three line variable two dimensional flicker filter is formed by summing the unit impulse function with a vertical flicker function scaled by FLK (Flicker Coefficient) and the peaking function which is scaled by SHP (Sharpness Coefficient). The FLK and SHP variables have 5 bits of resolutions, with a usable a range from 0 to 21/32 for FLK, and 0 to 31/32 for SHP. The perception of flicker varies with the angle of the flicker source to the horizontal. Experimentally it was determined that the perceived flicker threshold was between 20 and 35 degrees. Above 35 degrees few viewers can notice a line flicker and below 20 degrees most viewers can. The vertical response of the flicker filter varies with the angle from horizontal and only modifies parts of the video input that contain flicker. The plot of the filter response is shown below at 0, 14, 27, and 45 degrees from horizontal.
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1 0 1 2 Gain in Decibels 3 4 5 6 7 8 9 10 0 0.1 0.2 0.3 0.4 0.5
Normalized Vertical Frequency
FLK = 0 FLK = 4 FLK = 8 FLK = 12 FLK = 16 FLK = 20
Figure 8: Two Dimensional Flicker Filter Response (FLK=0,4,8,12,16,20; SHP=0)
1 0 1 2 Gain in Decibels 3 4 5 6 7 8 9 10 0 0.1 0.2 0.3 0.4 0.5
Normalized Vertical Frequency
Horizontal 14 Degrees 27 Degrees 45 Degrees
Figure 9: FLK = 16, SHP = 8; Response at Horizontal, 14, 27, 45 Degrees
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1 0 1 2 Gain in Decibels 3 4 5 6 7 8 9 10 0 0.1 0.2 0.3 0.4 0.5
Normalized Vertical Frequency
Horizontal 14 Degrees 27 Degrees 45 Degrees
Figure 10: FLK = 16, SHP = 16; Response at Horizontal, 14, 27, 45 Degrees
5.2 Frame Store Controller
The Frame Store Controller (FSC) coordinates pixel data transfer between the FS400 and the Frame buffer. For normal operation, a 16 Mbit SDRAM is connected to the frame store controller port. Supported SDRAM parts include: NEC NEC Samsung Samsung LG MOSEL VITALIC Hyundai PD451616G5-A10 PD4516161AG5-A10B KM416S1120A-G/F10 KM416S1020CT-F10 GM72V161621CT-10 V-54C316162T-10 HY57V161610BTC-10
The refresh of data in the SDRAM is accomplished through the continual update of the video output display. Therefore, any SDRAM selected must meet the frame rate maximum delay of the selected video. The worst case delay time is for PAL systems (25 frames/s) requiring a retention time of 40ms or greater. Data from the Capture Engine is written into the frame store in parallel with the extraction of data for the encoder engine. Read and write buffers at the data port allow data to be transferred in bursts without interruption of the overall flow of pixels. Bandwidth of the FSC bus is 80 MHz or 100 MHz, sufficient to support maximum rate write cycles from the Capture Engine simultaneously with full rate Encoder Engine read cycles.
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5.2.1 SDRAM Interface
The SDRAM Interface is designed to use a wide variety of 1Mx16 SDRAM parts. The critical parameters to use in selecting an SDRAM are listed below:
tFSSU tFSHO CLK tFSCO CS\ RAS\ CAS\ WE\ DQM\ tFSAO A[11:0] tFSDO D[15:0]
Figure 11. Timing Parameter Definition, SDRAM Interface
5.2.2 Phase Locked Loop
All SDRAM access is synchronized to the selected 4fSC clock derived from the OSC1 clock input. The 4fSC clock is divided by two, then depending upon the outgoing video standard selection, either NTSC or PAL, multiplied x9, x11, or x14 by the Frame Store Controller Phase Locked Loop to create the 80 or 100 MHz SDRAM clock.
5.2.3 Input Offset and Size Control
Besides synchronizing all SDRAM access activities, the frame store controller also coordinates several offset and size functions. These values are programmed into internal registers that control the setup of the Frame Store Controller. Input Horizontal Offset, IHO is an eleven bit value that sets the horizontal displacement of the captured active video relative to the horizontal sync as show in Figure 12.
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Input Vertical Offset, IVO is a twelve bit value that sets the vertical displacement of the captured active video relative to the vertical sync as show in Figure 12.
Incoming Vsynch
Figure 12. Input Offset and Size Definitions
Input Horizontal Active Width, IHAW is the 10-bit terminal count of the number of horizontal pixels to be inserted into frame store memory. (see Figure 12) Input Vertical Active Height, IVAH is the 11-bit terminal count of the number of vertical pixels to be inserted into frame store memory, which is equal to 2*ILS. (see Figure 12)
5.2.4 Output Offset and Size Control
Synchronization and timing of outgoing video pixel data is predetermined by the selection of the video format. However, the location of the active video area must be selected by programming the offset registers. Leading edges of outgoing horizontal and vertical sync define the dimensions of the outgoing frame as shown in Figure 13. Offsets OVO and OHO define the position of the active video area within the outgoing frame. Output Horizontal Offset, OHO is the 11-bit terminal count of the horizontal displacement of the outgoing active video in pixels relative to the leading edge of horizontal sync. (see Figure 13) Output Vertical Offset, OVO is the 10-bit terminal count of the vertical displacement of the outgoing active video in pixels relative to the beginning of vertical sync equalization pulses. (see Figure 13)
Figure 13. Output Horizontal and Vertical Offset Definitions
5.2.5 Freeze Frame
Setting the FREEZE bit of the Command Register can interrupt writing to the Frame Store. Capture will continue until the end of the current frame. 82
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5.2.6 Zoom
When zoom is activated by setting the ZOOM bit to 1 in the Command Register, pixels are 2X replicated in the vertical and the horizontal directions. Pixels are replicated vertically by the Capture Engine that duplicates the loading of each line into the Frame Store. If, for example, only 120 separate lines are accepted, then 240 lines are written to each field contained the Frame Store Memory. When the zoomed frame segment is retrieved, the number of horizontal pixels is doubled by duplicating each pixel twice as the pixels are read from the Frame Store Memory. IHAW should be set to 1/2 the non-zoomed IHAW. Offset may be applied to a zoomed image through the IHO and IVO registers as shown in Figure 14
Figure 14. Zoomed image showing offsets
5.3 Encoder Engine
5.3.1 Timing and Control
Timing of the Encoder Engine is synchronized by the Encoder Timing and Control Block. Frame store clock, RAMCK_OUT is derived from the OSC1 clock by the SDRAM phase locked loop. A clock signal must always be applied to the default clock input, OSC1. Depending upon the outgoing TV standard requirements, one of many possible clock combinations can be selected as depicted in the table below. Output Standard NTSC and PAL NTSC only PAL only Super RGB NTSC only Super RGB PAL only NTSC and VGA or VGA only NTSC and SVGA or SVGA only NTSC and Progressive NTSC Progressive NTSC only 100Hz PAL only OSC1 14.31818 MHz 14.31818 MHz Connect to OSC2 14.31818 MHz 17.734475 MHz 14.31818 MHz 14.31818 MHz 14.31818 MHz 14.31818 MHz 17.734475 MHz
Table 4. Clock Connections
OSC2 17.734475 MHz VSSPF 17.734475 MHz 20.140 MHz 20.000 MHz 25.175 MHz 38.400 MHz 28.63636 MHz 28.63636 MHz 35.46895 MHz
If other combinations are desired (such as PAL and 100Hz), then OSC2 must be multiplexed with the different frequencies desired while OSC1 is connected to a 14.31818 MHz or 17.734475 MHz input. General principles apply as follows: * * * NTSC, VGA, SVGA, and Progressive NTSC assume a 14.31818 MHz clock on OSC1 PAL must be on OSC2 100Hz PAL interlaced assumes 17.734475 on OSC1 and 35.46895 on OSC2 83
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*
Multiplexing alternatives on OSC2 must be done with an external multiplexer (perhaps controlled by a GPO bit)
5.3.2 Horizontal Scaler
The Frame Store Controller passes pixels extracted from the external frame store memory to the Horizontal Scaler. Programming the HSC register sets horizontal scale factor. HSC is the Horizontal Scaling Coefficient, m that determines the horizontal scaling factor: HSF = (1 + m/128) With a range: 0 m 384; 1 HSF 1 + 384/128
5.3.3 Digital Video Encoder
For Composite Video and Y/C outputs, pixels from the Horizontal Scaler are routed to the Video Encoder. NTSC (SMPTE 170M) and PAL (CCIR 624) standards are preprogrammed into the Video Encoder to preset horizontal and vertical timing, subcarrier frequency, and chrominance phase. Setting the Command Register OFMT1-0 bits to 00 selects Composite Video and Y/C outputs, setting it to 01 selects RGB and bypasses the encoder, and setting it to 10 or 11 selects component YUV directly. Setting the Command Register TV_CLK1-0 selects the output clock mode per the table in the Command Register description (section 4.5.9). Setting the Command Register PROG_INT bit switches the output mode from interlaced (0) to progressive (1). Setting the Command Register PAL_NTSC bit switches the output mode from NTSC (0) to PAL (1). Command Register bit, CBP inserts a 18% (0.64 MHz for NTSC; 0.8 MHz for PAL) fSC bandpass filter centered at fSC following the chroma modulator. Command Register bit, LNTCH insert a luminance notch filter in the Y channel prior to the Composite Video summer and the Y output. The Brightness Coefficient (BRT) provides an offset adjustment in the Luma Encoder. BRT is a signed 8bit number. The Contrast Coefficient (CON) provides a luma gain adjustment in the Luma Encoder. Contrast has an implicit denominator of 32. The Color Saturation Coefficient (CSC) provides a gain adjustment in the Chroma Encoder. Saturation has an implicit denominator of 32.
5.3.4 YUV/RGB Matrix
For RGB outputs, pixels from the Horizontal Scaler are routed to the YUV/RGB matrix. Matrix coefficients are programmed by setting the OFMT1-0 bits in the Command Register. For a YUV output, the OFMT1-0 bits can be set to bypass the YUV/RGB matrix.
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5.3.5 Digital-to-Analog Converters
Three 10-bit D/A converters accept data from either the video encoder or the YUV-to-RGB transcoder. Each output is a current source connected to the analog VDDDA supply. Current is injected into external resistor to develop the output voltage. Typically the DC load is 37.5 formed from two 75 resistors and a low pass filter. A 75 load may be selected to minimize power dissipation. Peak output current of the D/A converters is established by VREF and an external resistor connected between RREF and ground. Peak current is approximately 11 times the current through the reference resistor. An internal 1.276 volt reference is buffered from VREF by a resistor, to enable VREF to be overridden by an external voltage. Output current may be calibrated by resistor selection or by setting a potentiometer attached to RREF. For 1.3 volt video, with a 37.5 load, the correct value of RT is 389. With a 75 load, the correct value of RT is 778 ohm. This calculation is shown in the following example:
RT = 1024 / 97 * VREF
V DAC R LOAD
RREF R1 VTIN R2
RT = 1024 / 97 * 1.276V
(1.3V 37.5)
RT = 389
Figure 15. RREF and VTIN Setup
VTIN can be developed by splitting RT into 2 resistors, R1 and R2, wired so that RT = R1+R2. To minimize DAC noise, a bypass capacitor must be connected from CBYPR to an adjacent VDDDA pin. Disabling the power supplied to unused D/A converters may conserve power. Command Register Extended bit COMPOFF controls Composite Video D/A converter power. Command Register Extended bit YCOFF controls Y/C D/A converter.
5.3.6 On-Screen Display (FS403 only)
The FS403 has a simple eight wire interface for an On Screen Display (OSD) interface. A single input line is available for R, G, and B, giving the OSD programmer a choice of the eight 100% amplitude, 50% saturation Color Bar colors. Another input enables the overlay of the OSD into the video path, with a fifth line to half the intensity of the overlaid VGA video for better OSD contrast. The chip also provides the Horizontal Sync, Vertical Sync, and 2Fsc clock for the microcontroller synchronization. The Zilog Z90211 and the Philips P83C055 families are directly supported. Because the microcontroller operates at half the speed of the FS403 video encoder, a horizontal pixel from the microcontroller will be replicated to form two pixels in the FS403. Since the FS403 input hold times cannot be met by the OSD, the inputs are buffered using the 2Fsc clock."
5.4 Serial Control Port (R-Bus)
All FS400 register access is via a 2-wire serial control interface. Either 7 or 10-bit addressing may be used with two addresses available for each type of addressing scheme. (see Table 5. Serial Port Addresses). Two signals comprise the bus: clock (SIOCLK) and bi-directional data (SIODATA). The FS400 acts as a slave for receiving and transmitting data over the serial interface. The maximum clock rate is 800 KHz. 85
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Data received or transmitted on the SIODATA line must be stable for the duration of the positive-going SIOCLK pulse. Data on SIODATA may change only when SIOCLK = L. An SIODATA transition while SIOCLK = H is interpreted as a start or stop signal.
Figure 16. Serial Port Read/Write Timing
Figure 17. Serial Interface - Typical Byte Transfer
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Figure 18. 7-bit Slave Address with Read/Write\ Bit
SDA SCL
1
1
1
1
0
A9
A8
R/W
ACK0
Figure 19. 10-bit address transfer, upper two bits
SDA SCL
ACK0
A7
A6
A5
A4
A3
A2
A1
A0
ACK1
Figure 20. 10-bit address transfer, lower eight bits
There are five steps within a serial bus cycle: 1. Start signal 2. Slave address byte 3. Pointer register address byte 4. Data byte to read or write 5. Stop signal When the serial interface is inactive (SIOCLK = H and SIODATA = H) communications are initiated by sending a start signal. The start signal (Figure 16, left waveform) is a HIGH-to-LOW transition on SIODATA while SIOCLK is HIGH. This signal alerts all slaved devices that a data transfer sequence is imminent. For 7-bit addressing, the first eight bits of data transferred after a start signal comprise a seven bit slave address and a single R/W bit (Read = H, Write = L). As shown in Figure 17, the R/W bit indicates the direction of data transfer, read from or write to the slave device. If the transmitted slave address matches the address of the FS400 (set by the state of the SIOA0 and SIOA10/7 input pins in Table 5. Serial Port Addresses, the FS400 acknowledges by bringing SIODATA LOW on the 9th SIOCLK pulse (see Figure 18). If the addresses do not match, the FS400 does not acknowledge. With 10-bit addressing (see Figure 19 and Figure 20), data is still transferred in 8-bit chunks. The upper two bits of the ten bit address are transferred as the lower two bits of the first byte along with the reserved sequence 11110 in the upper five bits and the R/W bit. The lower eight bits are transferred in the second byte without a R/W bit. Subsequent data reads or writes follow the 7-bit transfer sequences. For each byte of data read or written, the MSB is the first bit of the sequence.
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SIOA10/7 0 0 1 1
SIOA0 0 1 0 1
Address 4A 6A 224 276
Table 5. Serial Port Addresses
5.4.1 Data Transfer via Serial Interface
If a slave device, such as the FS400 does not acknowledge the master device during a write sequence, SIODATA remains HIGH so the master can generate a stop signal. If the master device does not acknowledge the FS400 during a read sequence, the FS400 interprets this as "end of data". SIODATA remains HIGH so the master can generate a stop signal. To write data to a specific FS400 control register, the 8-bit pointer must be loaded with the address of the target control register after the slave address has been established. Value of the pointer is the base address for subsequent write operations. The pointer address auto-increments by after each control register data transfer. If more bytes are transferred than there are available addresses, the address will not increment and remain at its maximum value of 6 and send an acknowledge signal, ACK. Data is read from the control registers of the FS400 in a similar manner, except that two data transfer operations are required: 1. 2. 3. 4. Write the slave address byte with bit R/W = L. Write the pointer byte. Write the slave address byte with bit R/W = H Read the control register indexed by the pointer.
Preceding each slave write, there must be a start cycle. Following the pointer byte there should be a stop cycle. Sequential registers may be accessed by repeated read cycles since pointer auto-increments after each byte transfer. After the last read, there must be a stop cycle comprising a LOW-to-HIGH transition of SIODATA while SIOCLK is HIGH. (see Figure 16, right waveform) A repeated start signal occurs when the master device driving the serial interface generates a start signal without first generating a stop signal to terminate the current communication. This is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines.
5.4.2 Serial Interface Read/Write Examples
Examples below show how serial bus cycles can be linked together for single and multiple register read and write access cycles. For sequential register accesses, each ACK handshake initiates further SIOCLK clock cycles from the master to transfer the next data byte. 5.4.2.1 Write to one control register * Start signal * Slave Address byte (R/W bit = LOW) * Pointer Address byte * Data byte to register * Stop signal
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5.4.2.2 Write to two consecutive control registers * Start signal * Slave Address byte (R/W bit = LOW) * Pointer Address byte * Data byte to register * Data byte to register (pointer address + 1) * Stop signal 5.4.2.3 Read from one control register * Start signal * Slave Address byte (R/W bit = LOW) * Pointer Address byte * Start signal * Slave Address byte (R/W bit = HIGH) * Data byte from register * Stop signal
5.4.2.4 Read from two consecutive data registers * Start signal * Slave Address byte (R/W bit = LOW) * Data byte to register * Start signal * Slave Address byte (R/W bit = HIGH) * Data byte from pointer address * Data byte from (pointer address + 1) * Stop signal
5.5 Embedded Microprocessor
The configuration of the FS400 can be set by either an external source driving the SIO interface or internally using the built-in micro-controller as both share the serial bus. If the external pin INTCPUEN is active, the internal microprocessor has control.
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6. Specifications
6.1 Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Power Supply Voltages VDD (Measured to VSS) VDDAD (Measured to VSSAD) VDDPA and VDDPF (Measured to VSSPA and VSSPF) VDDDA (Measured to VSSDA) VSSAD, VSSPA, VSS, VSSPA, VSSDA (delta) Digital Inputs 3.3 V logic applied voltage (Measured to VSS)2 Forced current 3, 4 Min -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -10.0 Typ 3.3 3.3 3.3 3.3 Max 4.6 4.6 4.6 4.6 0.5 VDD + 0.5 10.0 Unit V V V V V V mA
Analog Inputs Applied Voltage (Measured to VSSAD)2 -0.5 VDDDA + 0.5 V Forced current 3, 4 -10.0 10.0 mA Digital Outputs 3.3 V logic applied voltage (Measured to VSS)2 -0.5 VDD + 0.5 V Forced current 3, 4 -6.0 6.0 mA Short circuit duration (single output in HIGH state to 1 second ground) Temperature Operating, Ambient -20 110 C Junction 150 C Lead Soldering (10 seconds) 300 C Vapor Phase Soldering (1 minute)1 220 C Storage1 -65 150 C Electrostatic Discharge5 150 V Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. 5. EIAJ test method.
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6.2 Operating Conditions
Parameter VDD VDDAD, VDDDA VDDPA, VDDPF AGND VRT VIN VREF IREF Digital Power Supply Voltage A/D and D/A Supply Voltage PLLs Supply Voltage Analog Ground (Measured to DGND) Reference Voltage, Top Analog Input Range External Reference Voltage D/A Converter Reference Current (IREF = VREF/RREF, flowing out of the RREF pin) Reference Resistor, VREF = Nom DAC Total Output Load Resistance Ambient Temperature, Still Air Min 3.15 3.15 3.15 -0.1 0.5 0 Nom 3.3 3.3 3.3 0 0.75 1.276 3.15 Max 3.45 3.45 3.45 0.1 2.0 VRT Units V V V V V V V mA C
RREF RL TA
392 37.5 0 70
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6.3 Electrical Characteristics
Parameter Power Supply Currents IDD 3.3 volt current IDDAD 3.3 volt Analog current IDDDA 3.3 volt Analog current IDDPA 3.3 volt Analog current IDDPF 3.3 volt Analog current IDDT 3.3 volt Total Current Digital Inputs and Outputs CI Input Capacitance CO Output Capacitance IIH Input Current, HIGH IIL IILP Input Current, LOW Input Current, LOW with pull-up Conditions FSCK-IN = 80MHz ADXCK=40MHz ADXCK=40MHz ADXCK=40MHz ADXCK=40MHz CKNTSC=20MHz Min Typ 159 66 90 4 16 350 5 10 VDD = max., VIN = max. VDD = max., VIN = 0 V VDD = max., VIN = 0 V 10 10 200 -100 2.0 0.8 -2.0 2.0 2.4 0.4 4 12 1000 1.276 15 1.40 +150 2 15 15 -20 -80 Max Unit mA mA mA mA mA mA pF pF A A A V V mA mA V V pF pF k A V A V k pF mA
VIHTTL Input Voltage, Logic HIGH (TTL) VILTTL Input Voltage, Logic LOW (TTL) IOH Output Current, Logic HIGH IOL Output Current, Logic LOW VOH Output Voltage, HIGH IOH = -2mA VOL Output Voltage, LOW IOL = 2mA Analog Inputs CAI A/D Input Capacitance ADCLK = LOW ADCLK = HIGH RIN A/D Input Resistance ICB A/D Input Current VRO Voltage Reference Output Internal Reference IRO VREF Output Current External VREF Analog Outputs VOC Video Output Compliance ROUT Video Output Resistance COUT Video Output Capacitance COUT = 0 mA, Freq. = 1 MHz IOS Short-Circuit Current
500 1.15 -150 -0.4
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6.4 Switching Characteristics
Parameter Clocks fCKIN_N NTSC Reference Clock Frequency fCKIN_P PAL Reference Clock Frequency fXTOL Reference Clock Frequency Tolerance tPWH Reference Clock Pulse Width, HIGH tPWL Reference Clock Pulse Width, LOW Reset Assert time on RESET to reset the part Incoming Syncs fH HS_IN frequency fV VS_IN frequency NH Number of lines per frame tPWHS HS_IN Pulsewidth tVS-HS VS_IN to HS_IN Delay tDS Sync Delay (VGA Sync to Sync Out) Video Output tDOV Analog Output Delay (4fSC clock to Video Out) tR D/A Output Current Risetime (10% to 90%) tF D/A Output Current Falltime (90% to 10%) SKEW D/A to D/A Skew SDRAM Frame Buffer Interface tFCKL FS_CK pulse width, LOW tFCKH FS_CK pulse width, HIGH tFSCO FS_CK to RAS\, CAS\, WE\ DQM\ out delay tFDSU FS_CK to data setup time tFDHO FS_CK to data hold time tFDO FS_CK to data out delay tFAO FS_CK to address out delay Serial Microprocessor Interface tDAL SIOCLK Pulse Width, LOW tDAH SIOCLK Pulse Width, HIGH tSTAH SIODATA Start Hold Time tSTASU SIOCLK to SIODATA Setup Time (Stop) tSTOSU SIOCLK to SIODATA Setup Time (Start) tBUFF SIODATA Stop Hold Time Setup tDSU SIODATA to SIOCLK Data Setup Time tDHO SIODATA to SIOCLK Data Hold Time Conditions Min Typ1 14.31818 17.734475 50 40 40 8 24 50 100 1 0 100 30 10 10 3 100 130 4095 Max Unit MHz MHz ppm ns ns Clocks KHz Hz s ns ns ns ns ns ns ns ns ns ns ns ns ns 1.3 0.6 0.6 0.6 0.6 1.3 300 300 s s s s s s ns ns
502
-3 5.0 5.0 2.0 3.0 3.0 2.0 2.0
0
Notes: 1. Values shown in Typ column are typical for VDD = VDDA = +3.3V and TA = 25C 2. TV subcarrier acceptance band is 300 Hz.
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6.5 System Performance Characteristics
Parameter A/D Converter Input ELI A/D Integral Linearity Error, Independent ELD A/D Differential Linearity Error EOT Offset Voltage, Top EOB Offset Voltage, Bottom Conditions VRT = 0.7V VRT = 0.7V VRT - VIN for most positive code transition VIN for most negative code transition Min Typ1 1 1 150 150 Max Unit LSB LSB mV mV
D/A Converter Output RES D/A Converter Resolution 10 Notes: 1. Values shown in Typ column are typical for VDD = VDDA = +3.3V and TA = 25C
10
10
Bits
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7. Application Notes
7.1 Circuit Example - PC
RGB video signals and the vertical and horizontal sync signals are intercepted by tapping connections to the VGA connector. Typically, control of the FS400 will be through the serial interface. S-video and Composite Video outputs are fed to connector that should be located at the board edge. Power is derived from +3.3 volt analog and digital supplies. It is recommended that the analog supply be clean of noise. Input impedance of the A/D converters exceeds 500K and will not load VGA RGB lines. Shunt 100pF capacitors and 110 series resistors form a low pass filter with 15 MHz cutoff. Filtering the incoming video has two functions: 1. equalizing the intensities of vertical lines 2. eliminating sampling noise. Outgoing video is filtered by low pass Bessel filters with 10 MHz cutoff. An optional low pass filter has two functions: 1. removal of steps from the Composite Video output 2. limiting the bandwidth of outgoing video. For higher definition of horizontal frequencies, a sinx/x correction filter should be incorporated to compensate for 1 dB sampling loss of the D/A converters. Schottky diode clamps protect the FS400 from high voltage transients.
10.00 0.00 -10.00 -20.00 -30.00 -40.00 1 10 Frequency (MHz)
Figure 21. Video Filter Response
Gain (dB)
100
50.00 40.00 30.00 20.00 10.00 0.00 1 10 Frequency (MHz)
Figure 22. Video Filter Delay
Delay (ns)
100
VTIN is derived from the bias voltage across RREF that is established by the internal reference voltage available at VREF. RREF is split into two resistors with series resistance to set the RREF current and ratio to establish the VTIN voltage. 95
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7.2 FS400 Design and Layout Considerations
Careful circuit design and layout are key factors that insure a successful implementation of the FS400 in a product. The following guidelines will help insure that your design yields the best possible results.
7.2.1 Video Input to A-D Converters
* Consider using a higher capacitor value and a lower resistor value in the input filter. For example, use 100 and 100pF instead of 220 and 47pF. This will reduce noise at the ADC input. * Place the input lowpass filter shunt capacitor as close as possible to the input pin on the FS400. This capacitor acts as a reservoir of charge for the ADC's input sampling circuitry, and limits the voltage kickback from the sampling process. * Make the video input traces to the A-D converters as short as possible. Do not route other signal traces (especially clocks!) parallel to these traces, or close to the ADC inputs of the FS400. External interference coupled into the video can easily be discerned by the eye at very low levels. * Consider adding diodes to VDDAD and VSSAD on these lines to reduce the risk of ESD damage to the FS400.
7.2.2 Input ADC Phase Lock Loop
* The analog supply for the ADC PLL should always be clean and noise free to insure minimum jitter in the PLL. This applies regardless of the PLL used, internal or external. Do not power other circuitry from the PLL supply. * When using the internal PLL, the supply line VDDPA should be decoupled with a series resistor of 150 and a 4.7F tantalum capacitor. If 50/60Hz ripple is an issue, consider using 47 or 100F. Always have a 1000pF to 0.1F capacitor to remove high frequency noise. * Do not run other traces (especially clocks) near an external PLL. * Use a solid ground plane under the FS400.
7.2.3 Memory Clock Phase Lock Loop
* When using an external PLL for the memory clock, series terminate the clock line, and keep the traces as short as possible to reduce EMI. * Avoid using an even multiple of the 4fSC clock as your memory clock. This increases EMI since multiples of the clocks that overlap are additive.
7.2.4 External SDRAM Interface
* Keep the traces from the FS400 to the external SDRAM as short as possible. Series terminate the RAS\, CAS\, and FSCK_OUT as close as possible to the FS400. Consider series terminating the address lines as well for further EMI reduction. * Keep other traces, especially analog traces, away from the traces associated with the SDRAM. In addition to 0.1F bypass capacitors, consider adding 100 to 1000pF capacitors to reduce higher frequency noise on the power supply.
7.2.5 HSYNC and VSYNC
* The HSYNC and VSYNC inputs to the FS400 should be low pass filtered. 150 and 100pF work well. Consider termination on these lines if the input cable length gives rise to significant reflections, undershoot and overshoot. * Consider adding diodes to VDD and VSS on these lines to reduce the risk of ESD damage to the FS400. 96
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7.2.6 Video Output Filters
* To reduce step noise on the D/A converter outputs, and to lower EMI, consider placing the 75 termination resistors and the first capacitor of the output filter close to the video output pins of the FS400.
7.2.7 Analog Power Supply Bypassing, Filtering, and Isolation
* When possible, it is recommended that the analog supply voltages be fed from a linear voltage regulator. Switching power supply noise, and noise from the digital plane can induce visible artifacts into the displayed video. Always provide sufficient filtering and high frequency bypassing to insure that power supply noise is minimized for visual as well as EMI reasons. * Noise from the digital plane must be kept isolated from the analog plane. Consider using a 1 to 2 resistor with a 100F capacitor as a filter network. The voltage drop to the analog plane is minimal, and this effectively minimizes clock noise from the digital plane. * It is recommended that each power supply section be isolated with a ferrite bead and a 4.7F capacitor. Where the power pins are so close together that the 0.1F bypass capacitors are adjacent, consider changing one of the adjacent capacitors to 100 to 1000pF to reduce higher frequency noise on the power supply.
7.2.8 Power and Ground
Within the FS400, separate power is routed to functional sections: A/D converters, phase locked loops, D/A converters, digital processors and digital drivers. To minimize power consumption, a +3.3 volt supply is used for the external SDRAM interface and the internal line buffers. All ground pins should be connected to a common ground plane. Power pins should be segregated into analog and digital sections. Clean analog power should be applied to the VDDAD, VDDPA, VDDPF, and VDDDA pins. A 0.1 F capacitor should be placed adjacent to each group of pins. The capacitor connected to CBYPR is critical, and it must be connected to VDDDA to minimize noise at the D/A converter outputs. Chip capacitors are recommended. Digital power may be derived from system digital +3.3 volts. If necessary insert a ferrite bead in series with the supply trace. A 47 F capacitor should be placed across the common +3.3 VDC for VDD, VDDAD and VDDDA to act as a reservoir for heavy currents drawn by D/A converters and memory. At least one 0.1 F capacitor should be located adjacent to VDD pins along each side of the FS400 to supply transient currents.
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7.3 Interfacing to the FS400 in a Mixed Voltage Environment
As many devices designed today, the FS400 is powered by +3.3 Volts. However, 5 Volt devices are still very common today and will continue to be used for some time in the future. To meet this interface requirement the FS400 has 5 Volt tolerant inputs. Unfortunately, the FS400 does not have 5 Volt tolerant outputs. When a bi-directional I/O pin is used on the FS400, care must be taken when driving the device.
7.3.1 5 to 3.3 Volt Translation
A series resistor is the simplest way to safely drive an I/O pin of the FS400 . This input resistor limits the input current to under the 10mA maximum limit when the input is raised towards the 5 Volt supply.
+5V R1 270
+3.3V
5 Volt Device
FS400
Figure 23. 5 to 3.3 Volt Translation using a Resistor
In applications where a series resistor limits the speed or the drive capability of the I/O, a pass gate can be used instead of a resistor. The pass gate (Q1) provides a low impedance path between the devices when the switching voltage is low and a high impedance path as the switching voltage approaches the supply rail. In the circuit below, D1 biases the gate of the MOSFET (Q1) down to 4.3 Volts so Q1 will turn off when its input exceeds 3.3 Volts. This limits the high state input current, into the FS400, to under the 10mA maximum value. Note that the MOSFET source is connected to the lower supply device and the MOSFET drain is connected to the higher supply device. This configuration reverse biases the MOSFET drain to bulk diode in the high switching state.
+5V
D1
R1 3.9K +3.3V
5 Volt Device
FS400
Q1
Figure 24. 5 to 3.3 Volt Translation using a MOSFET Q1 = BSS138, D1 = 1N4148
7.3.2 SIO Bus Interfacing
The SIO bus was developed previous to 3.3V logic processes. The SIO bus input voltage specification is 1.5 Volts for VIL and 3.0 Volts for VIH. The FS400 is built on a 3.3 Volt process and has 5 Volt tolerant inputs with a VIL of 0.8 Volts and a VIH of 2.0 Volts.
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For most applications this voltage difference is not an issue as the output drive low specification (VOL) of the SIO bus and the FS400 are both 0.4 Volts. However, in heavily loaded SIO busses the output VOL is not always preserved. An easy way to regain the 0.7 Volt difference in the VIL specification of the FS400 and the SIO bus is to bias the FS400's input negative by a diode drop (D1). The diode can be biased by a long-tail resistor pair or a current source pair. Shown below is the long-tail pair:
+12V
R1 22K To I2C D1 To FS400 R2 27K
-12V
Figure 25. SIO Translation Using Long-tail Resistors D1 = 1N4148
The long-tail pair is a simple circuit but has the disadvantage of requiring higher voltage power supplies. Also, these supplies may have to power up in a specific sequence so the surround circuits are not overvoltage. The translation circuit below requires only one 5 Volt power supply and has no special sequence requirements. In addition, the circuit offers a high impedance load (Q1 become reverse biased) to the SIO bus when its power supply is removed. Unfortunately, it requires more parts. In applications where transistors are more readily available, R2 and R3 can be replaced with diode connected transistors.
+5V
R1 2.9K
Q1 To I2C
R2 1.3K
D1 R3 1.2K Q2 To FS400
Figure 26. SIO Translation Using Current Mirrors D1 = 1N4148, Q1 = 2N3906, Q2 = 2N3904
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For applications with more than one supply, combinations of the above two circuits can be used. However, the simplest approach to this problem is to limit the loading on the SIO bus when possible. When this is not possible, some of the SIO passive loads can be replaced with active ones. This will increase the SIO access speed without increasing the SIO output low drive current. In lightly loaded SIO busses (where VOL is easily reached), a single MOSFET can be used for translation on the SIO SDA line (Since the FS400's input for SCL is 5 Volt tolerant, no additional parts are required on that input). Pull-ups on both supply sides assure that the output on each device can reach its corresponding upper limit. The pass gate (Q1) provides a low impedance connection during the low switching voltage.
+3.3V
+5V
R1 10K
FS400 OC Output
R2 10K
5 Volt Device OC Output
Q1
Figure 27. SIO (Open Collector) Translation using a MOSFET Q1 = BSS138
Q1 also provides isolation when the 3.3 Volt power to the FS400 is removed. The pass gate (Q1) gate to source voltage is negative and the bulk diode is off. This effectively removes the FS400's Serial Data line from the SIO bus system and allows the higher voltage SIO section to operate normally.
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8. Mechanical Dimensions
8.1 100-Lead PQFP (KH) Package - FS401LF
Package is RoHS Compliant.
Symbol A A1 A2 B C D D1 E E1 e L N ND NE ccc
Millimeters Min. Max. 3.00 0.05 2.55 2.75 0.25 0.40 0.10 0.25 23.60 24.20 19.80 20.20 17.30 18.20 13.80 14.20 0.65 BSC 0.60 1.00 100 30 20 0 8 -
Notes Notes: 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Controlling Dimension is millimeters 3. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 4. "L" is the length of terminal for soldering to a substrate. 5. "b" & "C" include lead finish thickness.
3,5 5
4
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8.2 128-Lead PQFP Package, FS403 LF
Package is RoHS Compliant.
Symbol A A1 B D D1 E E1 e L N ND NE
FS403LF Min. Max. 3.40 0.25 0.13 0.28 23.20 BSC 19.80 20.00 17.2 BSC 13.80 14.10 0.50 BSC 0.73 1.03 128 38 26
Notes: 6. All dimensions and tolerances conform to ANSI Y14.5M-1982. 7. Controlling Dimension is millimeters 8. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 9. "L" is the length of terminal for soldering to a substrate. 10. "B" includes lead finish thickness.
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FS401, FS403 REV. NO. 1.7
9. Revision History
3/3/99: First Release, V1.0 4/2/99: Second Release, V1.1: p. 1, added DPMS support & adaptive input filtering selection; p. 13, added GPO0 description; p. 17, moved OHO & OVO to list of registers used by on-board processor; p. 19-24, corrected typo on register names & added better DSICAL description; p. 66, added reminder about loop delay. 7/16/99: Third Release, V1.2: p. 10, 11, 16: documented need to ground "reserved" pins; p. 11 & 13, EXADSEL sense changed from early silicon to high true input (high selects external A/D on FS403); p. 19-24, corrected typo on register names & added better DSICAL description, description of new SCR bits, new HOHOS & HOVOS registers, SFLK change from register to bits in SCR; p. 26-27, new software reset values and new HOHOS, HOVOS registers & SCR bits; p. 38, proper VGAINTDET definition; p. 53, new SCR definitions; p. 55-57, new SSR, HCRS, and HCRES bit definitions; p. 58-63, HPO, VPO, HSS, VSS, HPP, VPP all require up to 25ms (vs. 10ms) to calculate limits; ; p. 68-69, new HOHOS & HOVOS registers definitions; p. 71-73, new Configuration Register definitions; p. 87, comment about Philips vs. FOCUS SIO addressing added; p. 88, errors in table corrected (p. 15 was correct, not table 5); p. 103, part number change. 9/2/99: Fourth Release, V1.3: p. 13, documented internal pull-down on EXADSEL; p. 14, corrected CCOMP pull down; p. 96, deleted reference to FS_CKIN to FC_CKOUT resistor, resistor not recommended; p. 103, package marking. 7/25/00: Fifth Release, V1.4: p. 1, new patent received; p. 5, corrected reference to external VGACKIN source; p. 19 section 4.2.1.2, corrected first section regarding DSICAL bit (deleted reference to ICALRDY bit); p. 25, Status Port changed to Status Register; p. 84, corrected oscillator settings for Super NTSC and Super PAL; p. 91, 92: VREF changed to 1.276V typical, new min/max. 1/23/03: Sixth Release, V1.5: Table 2, corrected FS403 signal assignments on pin 24 (now G6) and pin 26 (now G4). Section 3, corrected descriptions of FS403 pin 24 (now G6) and pin 26 (now G4). Section 4.5.25, refined the definition of the GPO register. 11/27/05: Seventh Release, V1.6 Table 8.2 modified to include FS403LF dimensions. Removed unreferenced rows in that table. 01/17/2007: Eight Release, V1.7. Leaded versions of FS401 and FS403 discontinued - removed all references to leaded version of these parts . FS402 discontinued, all references to FS402 removed from data sheet. Page 8, section 1.5.3 (FS402 application description) deleted. Page 52, removed reference to FS402 in register 34 Description. Page 75, removed reference to FS402 in Figure 5 description. Page 85, clarification on last sentence in section 5.3.6. Page 101, removed reference to FS402 in section 8.1. Page 102, removed reference to FS403 (leaded version), updated package drawing to eliminate confusion on pin 1 location. Page 104, removed reference to parts 444-2121, 444-2122, 444-2123 (non ROHS compliant parts), updated corporate contact information.
103
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
FS401, FS403
PRODUCT SPECIFICATION REV. NO. 1.7
10. Ordering Information
Order Number 444-2121LF 444-2123LF Temperature Range 0C to 70C 0C to 70C Screening Commercial Commercial Package 100 Lead PQFP 128 Lead PQFP Package Marking FS401LF FS403LF
444-2121LF and 444-2123LF are RoHS compliant. Additionally, a FS400 Hardware Development Kit is available for purchase, Order # 444-2020.
10.1 Package Markings:
FOCUS Enhancements FS40XLF where X = 1 or 3.
Please forward suggestions and corrections as soon as possible to info@focusinfo.com. The information herein is accurate to the best of FOCUS' knowledge, but not all specifications have been characterized or tested at the time of the release of this document. Parameters will be updated as soon as possible and updates made available. For further information on the FS400 family of scan converters, contact your Focus representative and request reference schematics, application notes, and source code (as appropriate).
All parameters contained in this specification are guaranteed by design, characterization, sample testing or 100% testing as appropriate. Focus Enhancements reserves the right to change products and specifications without notice. This information does not convey any license under patent rights of Focus Enhancements, Inc. or others.
Critical Applications Policy
Focus Enhancements components are not designed for use in Critical Applications. Critical Applications are products whose use may involve risks of death, personal injury, severe property damage or environmental damage or life support applications, devices, or systems, wherein a failure or malfunction of the component can reasonably be expected to result in death or personal injury. The user of Focus Enhancements components in Critical Applications assumes all risk of such use and indemnifies Focus Enhancements against all damages.
Focus enhancements - Semiconductor Group
22867 NW Bennett St., Suite #200 Hillsboro, OR 97124 U.S.A. Phone: (503) 615-7700 104
JANUARY 24, 2007 COPYRIGHT (c) 1999 FOCUS ENHANCEMENTS, INC.
Fax: (503) 615-4232 Website: www.FOCUSsemi.com

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